| Title | S℡LAR: A Generic EM Side-Channel Attack Protection through Ground-Up Root-Cause Analysis |
| Publication Type | Conference Paper |
| Year of Publication | 2019 |
| Authors | Das, Debayan, Nath, Mayukh, Chatterjee, Baibhab, Ghosh, Santosh, Sen, Shreyas |
| Conference Name | 2019 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) |
| Keywords | CMOS integrated circuits, composability, critical encryption signature, critical signal radiation, cryptographic hardware, cryptography, EM leakage, EM probes, EM SCA attack, EM Side-channel attack, Encryption, entire crypto IP, entire cryptographic core, example cryptographic block, external attacker, frequency 40.0 MHz, Generic countermeasure, generic EM side-channel attack protection, Ground-up EM Leakage Modeling, ground-up root-cause analysis, high-resolution electromagnetic probes, higher-level metal layers, integrated circuit, Integrated circuit modeling, Intel 32 nm CMOS technology interconnect stack, Internet, low-level metal routing, low-overhead solution, lower-level metal layers, lower-level metal routing, Metals, Metrics, noninvasive attacker, noninvasive electromagnetic side-channel attacks, power side-channel countermeasures, Probes, pubcrawl, resilience, Resiliency, resource-constrained Internet-connected devices, Routing, side-channel analysis attacks, signature attenuation embedded CRYPTO, signature attenuation hardware, size 32.0 nm, size 65.0 nm, S℡LAR, S℡LAR hardware, system-level EM simulations, system-level implementation, telecommunication network routing, top-level metal layers, TSMC 65 nm CMOS technology, two-stage solution, white box cryptography, white-box analysis, white-box understanding |
| Abstract | The threat of side-channels is becoming increasingly prominent for resource-constrained internet-connected devices. While numerous power side-channel countermeasures have been proposed, a promising approach to protect the non-invasive electromagnetic side-channel attacks has been relatively scarce. Today's availability of high-resolution electromagnetic (EM) probes mandates the need for a low-overhead solution to protect EM side-channel analysis (SCA) attacks. This work, for the first time, performs a white-box analysis to root-cause the origin of the EM leakage from an integrated circuit. System-level EM simulations with Intel 32 nm CMOS technology interconnect stack, as an example, reveals that the EM leakage from metals above layer 8 can be detected by an external non-invasive attacker with the commercially available state-of-the-art EM probes. Equipped with this `white-box' understanding, this work proposes S(tel)LAR: Signature aTtenuation Embedded CRYPTO with Low-Level metAl Routing, which is a two-stage solution to eliminate the critical signal radiation from the higher-level metal layers. Firstly, we propose routing the entire cryptographic core within the local lower-level metal layers, whose leakage cannot be picked up by an external attacker. Then, the entire crypto IP is embedded within a Signature Attenuation Hardware (SAH) which in turn suppresses the critical encryption signature before it routes the current signature to the highly radiating top-level metal layers. System-level implementation of the S(tel)LAR hardware with local lower-level metal routing in TSMC 65 nm CMOS technology, with an AES-128 encryption engine (as an example cryptographic block) operating at 40 MHz, shows that the system remains secure against EM SCA attack even after 1M encryptions, with 67% energy efficiency and 1.23x area overhead compared to the unprotected AES. |
| DOI | 10.1109/HST.2019.8740839 |
| Citation Key | das_slar_2019 |
S℡LAR: A Generic EM Side-Channel Attack Protection through Ground-Up Root-Cause Analysis