| Title | A New Pay-Per-Use Scheme for the Protection of FPGA IP |
| Publication Type | Conference Paper |
| Year of Publication | 2019 |
| Authors | Sun, Peiqi, Cui, Aijiao |
| Conference Name | 2019 IEEE International Symposium on Circuits and Systems (ISCAS) |
| Date Published | may |
| Keywords | application specific integrated circuits, complex FPGA designs, composability, copy protection, Design methodology, field programmable gate arrays, Field-Programmable Gate Arrays, finite state machine, finite state machines, FPGA IP protection, FPGA IP vendor, FSM, industrial property, IP infringement, IP instance, IP networks, ip protection, Licenses, logic design, pay-per-use, physical unclonable function, policy-based governance, pubcrawl, PUF, resilience, Resiliency, reusable intellectual property design blocks, security |
| Abstract | Field-programmable gate arrays (FPGAs) are widely applied in various fields for its merit of reconfigurability. The reusable intellectual property (IP) design blocks are usually adopted in the more complex FPGA designs to shorten design cycle. IP infringement hence becomes a concern. In this paper, we propose a new pay-per-use scheme using the lock and key mechanism for the protection of FPGA IP. Physical Unclonable Function (PUF) is adopted to generate a unique ID for each IP instance. An extra Finite State Machine (FSM) is introduced for the secure retrieval of PUF information by the FPGA IP vendor. The lock is implemented on the original FSM. Only when the FPGA developer can provide a correct license, can the FSM be unlocked and start normal operation. The FPGA IP can hence be protected from illegal use or distribution. The scheme is applied on some benchmarks and the experimental results show that it just incurs acceptably low overhead while it can resist typical attacks. |
| DOI | 10.1109/ISCAS.2019.8702721 |
| Citation Key | sun_new_2019 |
A New Pay-Per-Use Scheme for the Protection of FPGA IP