industrial property

biblio

A Support Vector Machine Algorithm for PIR Special Processor

Submitted by aekwall on Mon, 12/14/2020 - 12:30pm

data processing algorithm
timing design
SVM classification
real-time intellectual property core
pyroelectric infrared sensor
pyroelectric detectors
PIR special processor
PIR sensor
mathematical statistics
infrared products
human motion detection technology
function design
fast Fourier transform
distance 15.0 m
Support vector machines
continuous improvement
algorithm flow
IP core
hardware description languages
Kalman filters
Predictive Metrics
data acquisition
industrial property
microcontrollers
composability
pubcrawl
Resiliency
support vector machine

biblio

Attacking Split Manufacturing from a Deep Learning Perspective

Submitted by aekwall on Mon, 11/09/2020 - 1:42pm

integrated circuit split manufacturing
integrated circuit manufacture
Foundries
back-end-of-line parts
BEOL connections
different foundries
FEOL facility
front-end-of-line
image-based features
IP piracy
ISCAS-85benchmarks
layout-level placement
Metals
network-flow attack
security promise
sophisticated deep neural network
vector-based features
neural nets
invasive software
computer architecture
learning (artificial intelligence)
Resiliency
pubcrawl
composability
policy-based governance
deep learning
security of data
manufacturing systems
Capacitance
industrial property
Image Processing
Wires
Layout
Pins

biblio

A Cellular Automata Guided Obfuscation Strategy For Finite-State-Machine Synthesis

Submitted by aekwall on Mon, 11/09/2020 - 1:41pm

reverse engineering
testable key-controlled FSM synthesis scheme
state-transition
reverse engineering attacks
nongroup additive cellular automata
finite-state-machine synthesis
digital system
D1*CAdual
D1*CA
cellular automata guided obfuscation strategy
ip protection
IP piracy
cellular automata
security
flip-flops
Additives
finite state machines
Silicon
automata
industrial property
Logic gates
policy-based governance
composability
pubcrawl
Resiliency

biblio

Enhanced Functional Obfuscation of DSP core using Flip-Flops and Combinational logic

Submitted by aekwall on Mon, 11/09/2020 - 1:40pm

block logic
Trojan insertion
IP core locking block logic
Intellectual Property cores
Integrated Circuit design flow
ILB
hardware threats
functionally obfuscated design
functional obfuscation based security mechanism
functional obfuscation
flip-flops
flip-flop
DSP design
digital signal processing core
consumer electronics systems
combinational logic
Cryptography
IP core
IC design flow
IP piracy
Consumer electronics
combinational circuits
DSP
logic design
DSP core
digital signal processing chips
industrial property
policy-based governance
composability
pubcrawl
Resiliency

biblio

Hardware Steganography for IP Core Protection of Fault Secured DSP Cores

Submitted by aekwall on Mon, 11/09/2020 - 1:40pm

DSP based IP cores
vendor defined signature
transient fault secured IP cores
signature size
signature free approach
multimedia cores
IP core protection
IP core
high level synthesis
hardware steganography
fault secured DSP cores
Fault secure
entropy value
entropy thresholding
encoding rule
Resiliency
colored interval graph
IP piracy
Steganography
DSP
logic design
digital signal processing chips
Watermarking
industrial property
digital signatures
Entropy
graph theory
policy-based governance
composability
pubcrawl

biblio

A Novel PUF based Logic Encryption Technique to Prevent SAT Attacks and Trojan Insertion

Submitted by aekwall on Mon, 11/09/2020 - 1:33pm

intellectual property/IC
IP piracy
SAT attack
hardware obfuscation
Anti-Trojan insertion algorithm
Controllability
copy protection
design-for-trust
hardware Trojan insertion
HT insertion
hardware trojan
logic encryption methods
logic encryption techniques
logic locking
PUF based logic encryption technique
PUF-based encryption
Rare Signal
reverse engineering attack
unique encryption
Hardware Security
encryption
Hardware
invasive software
Resiliency
pubcrawl
composability
policy-based governance
Trojan horses
integrated circuits
Cryptography
Topology
Logic gates
industrial property
reverse engineering
integrated circuit design
logic circuits
Physical Unclonable Function
encryption key

biblio

Customized Locking of IP Blocks on a Multi-Million-Gate SoC

Submitted by aekwall on Mon, 11/09/2020 - 1:31pm

integrated circuit design
VLSI testing
Solid modeling
off-site untrusted fabrication facilities
multiple IP blocks
multimillion-gate SoC
IP block
integrated circuit manufacture
industrial designs
IP piracy
logic design
Erbium
IP networks
industrial property
Logic gates
integrated circuits
logic locking
policy-based governance
composability
pubcrawl
Resiliency
system-on-chip
security
Hardware

biblio

IC/IP Piracy Assessment of Reversible Logic

Submitted by aekwall on Mon, 11/09/2020 - 1:31pm

proper-size reversible functions
BDD
binary decision diagrams
embedded function
garbage outputs
IC-IP piracy assessment
IC/IP piracy
intellectual property piracy
Number of embeddings
ancillary inputs
QMDD
quantum multivalued decision diagrams
regular functions
Reversible logic
reversible logic circuits
reversible logic synthesis tools
IP piracy
IP networks
adiabatic computing
logic design
logic circuits
adders
Integrated circuit modeling
industrial property
Logic gates
quantum computing
Trojan horses
policy-based governance
composability
pubcrawl
Resiliency
embedded systems
security

biblio

A Comprehensive Security System for Digital Microfluidic Biochips

Submitted by grigby1 on Mon, 11/02/2020 - 1:36pm

private key cryptography
intellectual property security
invasive software
IP piracy
Lab-on-a-Chip
malicious attackers
Microfluidics
Pins
policy-based governance
intellectual property piracy
pubcrawl
resilience
Resiliency
secret keys
security
trojan
Trojan attacks
Trojan horses
comprehensive security system
authentication mechanism
bioassay completion time
biochips market
biology computing
bioMEMS
Cameras
CCD cameras
composability
authentication
Computer crime
defense mechanisms
Digital Microfluidic Biochips
Digital Microfluidics
DMFBs
Electrodes
Foundries
industrial property

biblio

Security-Driven Task Scheduling for Multiprocessor System-on-Chips with Performance Constraints

Submitted by grigby1 on Mon, 11/02/2020 - 1:36pm

pubcrawl
two-stage performance-constrained task scheduling algorithm
Trojan horses
task scheduling
Task Analysis
system-on-chip
System performance
system level security constraints
security-driven task scheduling
security of data
security
scheduling
Schedules
schedule length
Resiliency
resilience
composability
Processor scheduling
policy-based governance
performance constraints
Multiprocessor System-on-Chips
multiprocessing systems
MPSoC
malicious inclusions
logic design
IP networks
intellectual property security
industrial property
hardware trojan
Hardware
graph theory
delays

1
2
3
4
5
6
next ›
last »

Cyber-Physical Systems Virtual Organization

Read-only archive of site from September 29, 2023.

industrial property

A Support Vector Machine Algorithm for PIR Special Processor

Attacking Split Manufacturing from a Deep Learning Perspective

A Cellular Automata Guided Obfuscation Strategy For Finite-State-Machine Synthesis

Enhanced Functional Obfuscation of DSP core using Flip-Flops and Combinational logic

Hardware Steganography for IP Core Protection of Fault Secured DSP Cores

A Novel PUF based Logic Encryption Technique to Prevent SAT Attacks and Trojan Insertion

Customized Locking of IP Blocks on a Multi-Million-Gate SoC

IC/IP Piracy Assessment of Reversible Logic

A Comprehensive Security System for Digital Microfluidic Biochips

Security-Driven Task Scheduling for Multiprocessor System-on-Chips with Performance Constraints