| Title | Boot time Bitstream Authentication for FPGAs |
| Publication Type | Conference Paper |
| Year of Publication | 2019 |
| Authors | Siddiqui, A. S., Gui, Y., Saqib, F. |
| Conference Name | 2019 IEEE 16th International Conference on Smart Cities: Improving Quality of Life Using ICT IoT and AI (HONET-ICT) |
| Date Published | oct |
| Keywords | authentication, composability, cyber-physical system security, Encryption, field programmable gate arrays, Hardware, neural style transfer, Predictive Metrics, pubcrawl, Resiliency, Runtime, Scalability, Software, trusted platform modules |
| Abstract | Major commercial Field Programmable Gate Arrays (FPGAs) vendors provide encryption and authentication for programmable logic fabric (PL) bitstream using AES and RSA respectively. They are limited in scope of security that they provide and have proven to be vulnerable to different attacks. As-such, in-field deployed devices are susceptible to attacks where either a configuration bitstream, application software or dynamically reconfigurable bitstreams can be maliciously replaced. This hardware demo presents a framework for secure boot and runtime authentication for FPGAs. The presented system employs on-board cryptographic mechanisms and third-party established architectures such as Trusted Platform Module (TPM). The scope of this hardware demo is of systems level. |
| DOI | 10.1109/HONET.2019.8907956 |
| Citation Key | siddiqui_boot_2019 |
Boot time Bitstream Authentication for FPGAs