| Title | Exploiting Dual-Rail Register Invariants for Equivalence Verification of NCL Circuits |
| Publication Type | Conference Paper |
| Year of Publication | 2020 |
| Authors | Le, Son N., Srinivasan, Sudarshan K., Smith, Scott C. |
| Conference Name | 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS) |
| Keywords | asynchronous circuits, compositionality, equivalence checking, formal methods, formal verification, Industries, Logic gates, NULL Convention Logic, Predictive Metrics, pubcrawl, Rails, Registers, Resiliency, Scalability, scalable verification, Synchronization, Wires |
| Abstract | Equivalence checking is one of the most scalable and useful verification techniques in industry. NULL Convention Logic (NCL) circuits utilize dual-rail signals (i.e., two wires to represent one bit of DATA), where the wires are inverses of each other during a DATA wavefront. In this paper, a technique that exploits this invariant at NCL register boundaries is proposed to improve the efficiency of equivalence verification of NCL circuits. |
| DOI | 10.1109/MWSCAS48704.2020.9184477 |
| Citation Key | le_exploiting_2020 |
Exploiting Dual-Rail Register Invariants for Equivalence Verification of NCL Circuits