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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
asynchronous circuits
biblio
Exploiting Dual-Rail Register Invariants for Equivalence Verification of NCL Circuits
Submitted by aekwall on Mon, 05/03/2021 - 1:13pm
Wires
NULL Convention Logic
equivalence checking
asynchronous circuits
scalable verification
formal methods
Rails
formal verification
Registers
Resiliency
Compositionality
Predictive Metrics
Scalability
Logic gates
Industries
Synchronization
pubcrawl
biblio
Hardware Trojan Insertion and Detection in Asynchronous Circuits
Submitted by grigby1 on Wed, 02/26/2020 - 4:38pm
neural network
Trojan horses
trojan horse detection
Trojan detection methods
synchronous hardware Trojan
supply chain security
Routing
Resiliency
resilience
Random Forest
pubcrawl
Pipelines
asynchronous circuit
logic design
Latches
hardware Trojan threats
hardware Trojan insertion
hardware trojan
Hardware
delays
deep learning
cyber physical systems
asynchronous hardware Trojan circuits
asynchronous circuits
biblio
A Machine Learning Attacks Resistant Two Stage Physical Unclonable Functions Design
Submitted by grigby1 on Mon, 06/10/2019 - 1:55pm
mirrors
Transistors
traditional approaches
stage physical unclonable functions design
security of data
security applications
security
Resiliency
resilience
Reliability
PUF
pubcrawl
privacy
physical unclonable function (PUF)
modelling attacks
32-bit current mirror
Mathematical model
machine learning attacks
machine learning
lightweight electronics
learning (artificial intelligence)
Hash functions
enhancing security
Current Mirror PUF
Cryptography
composability
CMOS integrated circuits
asynchronous circuits
Arbiter-PUF
65nm CMOS technology
