| Title | Architecting a Secure Wireless Interconnect for Multichip Communication: An ML Approach |
| Publication Type | Conference Paper |
| Year of Publication | 2020 |
| Authors | Ahmed, MMeraj, Vashist, Abhishek, Pudukotai Dinakarrao, Sai Manoj, Ganguly, Amlan |
| Conference Name | 2020 Asian Hardware Oriented Security and Trust Symposium (AsianHOST) |
| Date Published | Dec. 2020 |
| Publisher | IEEE |
| ISBN Number | 978-1-7281-8952-9 |
| Keywords | Communication system security, Computer architecture, Hardware, i-o systems security, jamming, Media Access Protocol, mm-wave, multichip, NoC, pubcrawl, Scalability, security, Wireless, Wireless communication |
| Abstract | Compute-intensive platforms such as micro-servers and embedded systems have already undergone a shift from a single-chip to multichip architecture to achieve better yield and lower cost. However, performance of multichip systems is limited by the latency and power-hungry chip-to-chip wired I/Os. On the other hand, wireless interconnections are emerging as an energy-efficient and low latency interconnect solution for such multichip systems as it can mask long multi-hop off-chip wired I/O communication. Despite efficient communication, the unguided on and off-chip wireless communication introduce security vulnerabilities in the system. In this work, we propose a reconfigurable, secure millimeter-wave (mm-Wave) wireless interconnection architecture (AReS) for multichip systems capable of detecting and defending against emerging threats including Hardware Trojans (HTs) and Denial-of-Service (DoS) using a Machine Learning (ML)-based approach. The ML-based approach is used to classify internal and external attack to enable the required defense mechanism. To serve this purpose, we design a reconfigurable Medium Access Control (MAC) and a suitable communication protocol to enable sustainable communication even under jamming attack from both internal and external attackers. The proposed architecture also reuses the in-built test infrastructure to detect and withstand a persistent jamming attack in a wireless multichip system. Through simulation, we show that, the proposed wireless interconnection can sustain chip-to-chip communication even under persistent jamming attack with an average 1.44xand 1.56x latency degradation for internal and external attacks respectively for application-specific traffic. |
| URL | https://ieeexplore.ieee.org/document/9358256 |
| DOI | 10.1109/AsianHOST51057.2020.9358256 |
| Citation Key | ahmed_architecting_2020 |
Architecting a Secure Wireless Interconnect for Multichip Communication: An ML Approach