| Title | SRTLock: A Sensitivity Resilient Two-Tier Logic Encryption Scheme |
| Publication Type | Conference Paper |
| Year of Publication | 2021 |
| Authors | Saxena, Nikhil, Narayanan, Ram Venkat, Meka, Juneet Kumar, Vemuri, Ranga |
| Conference Name | 2021 IEEE International Symposium on Smart Electronic Systems (iSES) |
| Date Published | dec |
| Keywords | 0-Injection, Benchmark testing, Encryption, Hardware, hardware security, Human Behavior, logic design, logic encryption, Logic gates, pattern locks, pubcrawl, resilience, Resiliency, SAT attack, Scalability, sensitivity analysis, Sensitivity Attack, Standards |
| Abstract | Logic encryption is a method to improve hardware security by inserting key gates on carefully selected signals in a logic design. Various logic encryption schemes have been proposed in the past decade. Many attack methods to thwart these logic locking schemes have also emerged. The satisfiability (SAT) attack can recover correct keys for many logic obfuscation methods. Recently proposed sensitivity analysis attack can decrypt stripped functionality based logic encryption schemes. This article presents a new encryption scheme named SRTLock, which is resilient against both attacks. SRTLock method first generates 0-injection circuits and encrypts the functionality of these nodes with the key inputs. In the next step, these values are used to control the sensitivity of the functionally stripped output for specific input patterns. The resultant locked circuit is resilient against the SAT and sensitivity analysis attacks. Experimental results demonstrating this on several attacks using standard benchmark circuits are presented. |
| DOI | 10.1109/iSES52644.2021.00095 |
| Citation Key | saxena_srtlock_2021 |
SRTLock: A Sensitivity Resilient Two-Tier Logic Encryption Scheme