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Hardware security, whether for attack or defense, differs from software, network, and data security in that attackers may find ways to physically tamper with devices without leaving a trace, and mislead the user to believe that the hardware is authentic and trustworthy. Furthermore, the advent of new attack modes, illegal recycling, and hard-to-detect Trojans make hardware protection an increasingly challenging task. Design of secure hardware integrated circuits requires novel approaches for authentication that are ideally based on multiple layers of protection. This project develops a novel framework for embedding heterogeneity and hierarchy in security and obfuscation at multiple layers into the design of integrated circuits.
The project uses a combination of server-based global authentication combined with local authentication of components from third-party vendors reduces communication with the server, thus reducing the communication overhead as well as error in authentication. The investigators explore new approaches to increasing robustness of SRAM based physical unclonable functions (PUFs) by intentional voltage stress, and the tradeoffs in hierarchies of authentication. The project investigates techniques for obfuscation based on modifications of finite state machine (FSM) state transition graphs, and obfuscation metrics that are developed and validated using data collected from test chips.
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SaTC: STARSS: Design of Secure and Anti-Counterfeit Integrated Circuits