A red team blue team approach towards a secure processor design with hardware shadow stack
| Title | A red team blue team approach towards a secure processor design with hardware shadow stack |
| Publication Type | Conference Paper |
| Year of Publication | 2017 |
| Authors | Bresch, C., Michelet, A., Amato, L., Meyer, T., Hély, D. |
| Conference Name | 2017 IEEE 2nd International Verification and Security Workshop (IVSW) |
| Publisher | IEEE |
| ISBN Number | 978-1-5386-1708-3 |
| Keywords | composability, Computer architecture, Computer bugs, embedded system security, Embedded systems, Hardware, hardware shadow stack, hardware-software codesign, memory corruption, Metrics, object oriented security, object-oriented programming, open processor architectures, openrisc, Payloads, private data access, processor architecture, processor design security, processor vulnerabilities, pubcrawl, red team blue team approach, reduced instruction set computing, resilience, Resiliency, return oriented programming attack, RISC-V, security, security of data, software attacks, Trusted Computing |
| Abstract | Software attacks are commonly performed against embedded systems in order to access private data or to run restricted services. In this work, we demonstrate some vulnerabilities of commonly use processor which can be leveraged by hackers to attack a system. The targeted devices are based on open processor architectures OpenRISC and RISC-V. Several software exploits are discussed and demonstrated while a hardware countermeasure is proposed and validated on OpenRISC against Return Oriented Programming attack. |
| URL | https://ieeexplore.ieee.org/document/8031545 |
| DOI | 10.1109/IVSW.2017.8031545 |
| Citation Key | bresch_red_2017 |
- private data access
- Trusted Computing
- software attacks
- security of data
- security
- RISC-V
- return oriented programming attack
- Resiliency
- resilience
- reduced instruction set computing
- red team blue team approach
- pubcrawl
- processor vulnerabilities
- processor design security
- processor architecture
- composability
- Payloads
- openrisc
- open processor architectures
- object-oriented programming
- object oriented security
- Metrics
- memory corruption
- hardware-software codesign
- hardware shadow stack
- Hardware
- embedded systems
- embedded system security
- Computer bugs
- computer architecture