Visible to the public A Study on the Effect of Hardware Trojans in the Performance of Network on Chip Architectures

TitleA Study on the Effect of Hardware Trojans in the Performance of Network on Chip Architectures
Publication TypeConference Paper
Year of Publication2021
AuthorsPhilomina, Josna
Conference Name2021 8th International Conference on Smart Computing and Communications (ICSCC)
KeywordsComputer architecture, electronics industry, Globalization, Hardware Trojans (HT), Metrics, multicore, multicore computing security, Multicore processing, Network on Chip (NoC), network on chip security, Program processors, pubcrawl, resilience, Resiliency, Scalability, System performance, Taxonomy, Tiled Chip Multicore Processors (TCMP)
AbstractNetwork on chip (NoC) is the communication infrastructure used in multicores which has been subject to a surfeit of security threats like degrading the system performance, changing the system functionality or leaking sensitive information. Because of the globalization of the advanced semiconductor industry, many third-party venders take part in the hardware design of system. As a result, a malicious circuit, called Hardware Trojans (HT) can be added anywhere into the NoC design and thus making the hardware untrusted. In this paper, a detailed study on the taxonomy of hardware trojans, its detection and prevention mechanisms are presented. Two case studies on HT-assisted Denial of service attacks and its analysis in the performance of network on Chip architecture is also presented in this paper.
DOI10.1109/ICSCC51209.2021.9528249
Citation Keyphilomina_study_2021