Title | Convolutional Compaction-Based MRAM Fault Diagnosis |
Publication Type | Conference Paper |
Year of Publication | 2021 |
Authors | Grzelak, Bartosz, Keim, Martin, Pogiel, Artur, Rajski, Janusz, Tyszer, Jerzy |
Conference Name | 2021 IEEE European Test Symposium (ETS) |
Keywords | built-in self-test, convolutional compaction, Cyber-physical systems, DfT, fault diagnosis, human factors, memory built-in self-test, Metrics, MRAM, multiple fault diagnosis, Ports (Computers), pubcrawl, Random access memory, Resiliency, Resistance, STT-MRAM, Systematics, Torque |
Abstract | Spin-transfer torque magnetoresistive random-access memories (STT-MRAMs) are gradually superseding conventional SRAMs as last-level cache in System-on-Chip designs. Their manufacturing process includes trimming a reference resistance in STT-MRAM modules to reliably determine the logic values of 0 and 1 during read operations. Typically, an on-chip trimming routine consists of multiple runs of a test algorithm with different settings of a trimming port. It may inherently produce a large number of mismatches. Diagnosis of such a sizeable volume of errors by means of existing memory built-in self-test (MBIST) schemes is either infeasible or a time-consuming and expensive process. In this paper, we propose a new memory fault diagnosis scheme capable of handling STT-MRAM-specific error rates in an efficient manner. It relies on a convolutional reduction of memory outputs and continuous shifting of the resultant data to a tester through a few output channels that are typically available in designs using an on-chip test compression technology, such as the embedded deterministic test. It is shown that processing the STT-MRAM output by using a convolutional compactor is a preferable solution for this type of applications, as it provides a high diagnostic resolution while incurring a low hardware overhead over traditional MBIST logic. |
DOI | 10.1109/ETS50041.2021.9465464 |
Citation Key | grzelak_convolutional_2021 |