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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
RTL design verification
biblio
A unified sequential equivalence checking approach to verify high-level functionality and protocol specification implementations in RTL designs
Submitted by BrandonB on Wed, 05/06/2015 - 2:44pm
high level functionality verification
unified sequential equivalence checking approach
Sequential equivalence checking
sequence of states
RTL design verification
RTL design
Protocols
protocol specification implementation
Integrated circuit modeling
high-level models
high level synthesis
high level reference model
high level model
Abstracts
formal verification
formal technique
Formal Specification
electronic design automation
Educational institutions
design verification
design under verification
Data models
Computational modeling
computational margin
communication protocol
Calculators
