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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
electronic design automation
biblio
A Graph Theory Approach towards IJTAG Security via Controlled Scan Chain Isolation
Submitted by grigby1 on Mon, 11/02/2020 - 11:28am
Registers
IJTAG network
IJTAG security
Instruments
intellectual property security
isolation signals
microprocessor chips
on-chip access
on-chip instruments
policy-based governance
power consumption
pubcrawl
IJTAG
resilience
Resiliency
scan chain
security
security of data
system-on-chip
system-on-chip designs
third party intellectual property providers
unauthorized user access
untrusted sources
Diagnosis
Clocks
Complexity theory
composability
controlled scan chain isolation
data integrity
Data Integrity Attacks
data manipulation
data protection scheme
data sniffing
debug
design for test
authorisation
electronic design automation
embedded instruments
embedded systems
graph coloring problem
graph colouring
graph theory approach
hidden test-data registers
IEEE standards
IEEE Std 1687
IEEE Std. 1687
biblio
Trends on EDA for low power
Submitted by grigby1 on Wed, 03/08/2017 - 12:54pm
state-of-the-art microprocessors
low-power electronics
microprocessor chips
optimization
Physical design
power consumption
Power demand
power optimization
pubcrawl170110
Low power
transistor circuits
transistor layout
transistor network
transistor sizing
Transistors
visualization
visualization tools
AD 2012
Logic gates
Libraries
layout design automation tool
Layout
ISPD Contest
integrated circuit layout
electronic design automation
EDA algorithms
EDA
discrete gate sizing
continuous gate sizing
cell library
Algorithms
Algorithm design and analysis
AD 2013
biblio
A unified sequential equivalence checking approach to verify high-level functionality and protocol specification implementations in RTL designs
Submitted by BrandonB on Wed, 05/06/2015 - 1:44pm
high level functionality verification
unified sequential equivalence checking approach
Sequential equivalence checking
sequence of states
RTL design verification
RTL design
Protocols
protocol specification implementation
Integrated circuit modeling
high-level models
high level synthesis
high level reference model
high level model
Abstracts
formal verification
formal technique
Formal Specification
electronic design automation
Educational institutions
design verification
design under verification
Data models
Computational modeling
computational margin
communication protocol
Calculators
