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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
hardware overhead
biblio
QIF-Verilog: Quantitative Information-Flow based Hardware Description Languages for Pre-Silicon Security Assessment
Submitted by grigby1 on Fri, 09/18/2020 - 1:15pm
pre-silicon security assessment
design stage
formal verification methods
hardware designer
hardware overhead
hardware system
hardware vulnerabilities
language based framework
language-based approach
language-based hardware security verification
malicious logic detection
potential security vulnerabilities
design mistakes
promising solution
QIF model
QIF-Verilog
quantified information flow model
quantitative information-flow
security rules
verification process
Verilog type systems
vulnerable logic detection
compiler security
integrated circuit testing
Hardware design languages
Cryptography
security solutions
security of data
security
pubcrawl
Metrics
resilience
Resiliency
Hardware
Integrated circuit modeling
hardware description languages
Scalability
Registers
integrated circuit design
formal verification
Measurement
Compositionality
uncertainty
Vulnerability Analysis
electronic engineering computing
data flow
biblio
A highly reliable and tamper-resistant RRAM PUF: Design and experimental validation
Submitted by grigby1 on Mon, 11/20/2017 - 11:28am
security
resilience
Resiliency
resistive RAM
resistive random access memory
RRAM
RRAM arrays
RRAM PUF instances
RRAM PUF properties
RRAM PUF resistance
Reliability
self-destructive feature
split reference
split S/A
split sense amplifier
Tamper resistance
tamper-resistant design
tamper-resistant RRAM PUF
top-level interconnect
uniqueness
invasive tampering
Decoding
dummy cells
extrapolation
Hardware
hardware overhead
Hardware Security
HD
inter-Hamming distance
interconnect layers
composability
layout obfuscation
layout obfuscation scheme
Logic arrays
multiple RRAM cells
Physical Unclonable Function
pubcrawl
PUF
relaxing transistor
