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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
bus interconnects
biblio
A hierarchical approach to self-test, fault-tolerance and routing security in a Network-on-Chip
Submitted by grigby1 on Fri, 05/15/2020 - 12:44pm
packet-switching
local self-test manager
malformed packets
malicious denial-of-service attack
malicious external agent
microprocessor chips
multiprocessing systems
network bandwidth
network-on-chip
NoC
on-chip networks
packet switching
local router
power virus
routing agent
routing security
security concerns
sorting-based algorithm
telecommunication network routing
test algorithms
two-tier approach
two-tier solution
virtual channel flow control
virtual channels
deadlock-free properties
Scalability
resilience
Resiliency
Metrics
associated physical channels
bus interconnects
chip multiprocessors
communication efficiency
computer network reliability
computer network security
deadlock situation
network on chip security
denial-of-service attacks
external source
fault data
fault tolerant computing
fault-information
fault-tolerance aspects
fault-tolerant routing
flit-switching
hierarchical approach
internet
local processing element
