Skip to Main Content Area
CPS-VO
Contact Support
Browse
Calendar
Announcements
Repositories
Groups
Search
Search for Content
Search for a Group
Search for People
Search for a Project
Tagcloud
› Go to login screen
Not a member?
Click here to register!
Forgot username or password?
Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
on-chip networks
biblio
A Benchmark Suite of Hardware Trojans for On-Chip Networks
Submitted by grigby1 on Fri, 05/15/2020 - 12:45pm
Information Leakage
Trojan horses
system-on-chip
standards
side channel analysis
security
Routing
performance degradation
on-chip networks
NoC
network-on-chip
multiprocessing systems
multicore systems
manycore systems
invasive software
network on chip security
HT defense methods
Hardware Trojans
hardware trojan
Hardware
Functional testing
Cryptography
benchmarks
Benchmark testing
benchmark suite
Metrics
Resiliency
resilience
Scalability
biblio
A hierarchical approach to self-test, fault-tolerance and routing security in a Network-on-Chip
Submitted by grigby1 on Fri, 05/15/2020 - 12:44pm
packet-switching
local self-test manager
malformed packets
malicious denial-of-service attack
malicious external agent
microprocessor chips
multiprocessing systems
network bandwidth
network-on-chip
NoC
on-chip networks
packet switching
local router
power virus
routing agent
routing security
security concerns
sorting-based algorithm
telecommunication network routing
test algorithms
two-tier approach
two-tier solution
virtual channel flow control
virtual channels
deadlock-free properties
Scalability
resilience
Resiliency
Metrics
associated physical channels
bus interconnects
chip multiprocessors
communication efficiency
computer network reliability
computer network security
deadlock situation
network on chip security
denial-of-service attacks
external source
fault data
fault tolerant computing
fault-information
fault-tolerance aspects
fault-tolerant routing
flit-switching
hierarchical approach
internet
local processing element
biblio
M3: A Hardware/Operating-System Co-Design to Tame Heterogeneous Manycores
Submitted by grigby1 on Tue, 05/30/2017 - 12:45pm
accelerators
capabilities
composability
heterogeneous architectures
linux operating systems security
Metrics
on-chip networks
operating systems
pubcrawl
Resiliency
