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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
packet switching
biblio
Dynamic Router's Buffer Sizing using Passive Measurements and P4 Programmable Switches
Submitted by aekwall on Mon, 03/14/2022 - 12:44pm
passive measurement
Switches
Size measurement
Router Systems Security
Resiliency
pubcrawl
programmable data planes
Production
Predictive Metrics
bandwidth-delay product
packet switching
P4 language
Instruments
delays
control systems
Congestion Control
Conferences
Buffer size
biblio
High-Performance and Range-Supported Packet Classification Algorithm for Network Security Systems in SDN
Submitted by grigby1 on Tue, 02/23/2021 - 1:38pm
packet header bits
512-bit OpenFlow rule
Bit Vector-based packet classification methods
content-addressable storage
high clock frequency
key function
multidimensional fields
multifield matching
network security systems
Clocks
packet switching
range fields
range matching
Range Supported Bit Vector algorithm
Range-Supported packet classification algorithm
RSBV
rule sets
two-dimensional modular architecture
Communication networks
IP networks
pubcrawl
Metrics
resilience
Resiliency
computer network security
Throughput
internet
security
composability
telecommunication network routing
encoding
pattern classification
SDN
software defined networking
pipeline processing
network coding
biblio
DoS attack mitigation in SDN networks using a deeply programmable packet-switching node based on a hybrid FPGA/CPU data plane architecture
Submitted by aekwall on Mon, 06/29/2020 - 11:57am
deeply programmable packet-switching node
SDN
Firewalls (computing)
DoS
Software-Defined Networks
5G
data plane
denial-of-service attack
denial-of-service attacks
architectural model
deep network programmability
software-defined networking
DoS attack mitigation
DoS attack redirection
DoS attacks mitigation
DoS traffic
DPN
packet switching
packet-switching nodes
switches price
DDoS attack mitigation
computer network management
DDoS
field programmable gate arrays
FPGA
firewall
telecommunication traffic
authorisation
Hardware
Software
computer architecture
computer network security
SDN network
software defined networking
Resiliency
Human behavior
pubcrawl
composability
Metrics
internet
Filtering
biblio
A hierarchical approach to self-test, fault-tolerance and routing security in a Network-on-Chip
Submitted by grigby1 on Fri, 05/15/2020 - 11:44am
packet-switching
local self-test manager
malformed packets
malicious denial-of-service attack
malicious external agent
microprocessor chips
multiprocessing systems
network bandwidth
network-on-chip
NoC
on-chip networks
packet switching
local router
power virus
routing agent
routing security
security concerns
sorting-based algorithm
telecommunication network routing
test algorithms
two-tier approach
two-tier solution
virtual channel flow control
virtual channels
deadlock-free properties
Scalability
resilience
Resiliency
Metrics
associated physical channels
bus interconnects
chip multiprocessors
communication efficiency
computer network reliability
computer network security
deadlock situation
network on chip security
denial-of-service attacks
external source
fault data
fault tolerant computing
fault-information
fault-tolerance aspects
fault-tolerant routing
flit-switching
hierarchical approach
internet
local processing element
biblio
Efficient Timing Channel Protection for Hybrid (Packet/Circuit-Switched) Network-on-Chip
Submitted by grigby1 on Fri, 05/15/2020 - 11:29am
Switching circuits
network transmission
network-on-chip
packet switching
packet switching NoC
packet-circuit-switched
security in NoC
Separate interface Hybrid
side-channel attacks
network routing
system security policy
TDM
Throughput
timing
timing channel
timing channel protection
timing characteristics
timing side channel
combined hybrid routers
network on chip security
Scalability
Resiliency
resilience
Metrics
channel attacks
circuit switching
circuit switching NoC
pubcrawl
conventional hybrid router
covert timing channel
hybrid network-on-chip
hybrid NoC
Integrated circuit modeling
MP-SoC
multiprocessing systems
multiprocessor system-on-chip
biblio
One more queue is enough: Minimizing flow completion time with explicit priority notification
Submitted by grigby1 on Wed, 02/21/2018 - 12:49pm
Resiliency
packet switching
policy governance
Policy-Governed Secure Collaboration
Processor scheduling
pubcrawl
queue
queueing theory
resilience
Metrics
scheduling
scheduling mechanism
switch priority queues
Switches
TCP
telecommunication traffic
transport protocols
fine-grained priorities
clean slate
clean-slate switch hardware
collaboration
commodity switches
computer centres
Conferences
Dynamic scheduling
EPN
Bandwidth
flow completion time
flow scheduling
flow size information
Hardware
Human behavior
human factor
Human Factors