Skip to Main Content Area
CPS-VO
Contact Support
Browse
Calendar
Announcements
Repositories
Groups
Search
Search for Content
Search for a Group
Search for People
Search for a Project
Tagcloud
› Go to login screen
Not a member?
Click here to register!
Forgot username or password?
Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
hardware accelerators
biblio
Breaking a fully Balanced ASIC Coprocessor Implementing Complete Addition Formulas on Weierstrass Elliptic Curves
Submitted by aekwall on Mon, 02/15/2021 - 3:56pm
Elliptic curve cryptography (ECC)
Weierstrass elliptic curves
side channel analysis (SCA) attacks
random order execution
point doubling operations
point addition
open-source designs
Montgomery ladder
horizontal SCA attacks
horizontal DPA attacks
hardware accelerators
fully balanced ASIC coprocessor
complete addition formulas
Scalability
application specific integrated circuits
coprocessors
Clocks
logic design
Registers
Elliptic curves
Elliptic curve cryptography
public key cryptography
Metrics
pubcrawl
Resiliency
biblio
C3APSULe: Cross-FPGA Covert-Channel Attacks through Power Supply Unit Leakage
Submitted by grigby1 on Wed, 02/10/2021 - 11:52am
potentially unintentional interactions
FPGA-to-FPGA
FPGAs
GPU-to-FPGA covert channels
hardware accelerators
highly-sensitive data
independent boards
Kintex 7 FPGA chips
local cloud FPGA
off-the-shelf Xilinx boards
per-user basis
potential countermeasures
FPGA security
Power Attacks
power supply unit leakage
Power supply units
receiving circuits
reconfigurable integrated circuits
Ring oscillators
sensing stressing ring oscillators
shared infrastructures
shared power supply units
sink FPGA
source FPGA
covert channels
pubcrawl
resilience
Resiliency
field programmable gate arrays
Hardware
Scalability
cloud environments
Compositionality
Voltage measurement
Transmitters
cryptographic keys
Cryptography
Field-Programmable Gate Arrays
Temperature measurement
Voltage control
Voltage regulators
APSULe
CPU-to-FPGA
cross-board leakage
cross-FPGA covert-channel attacks
data center infrastructure
different data center tenants
biblio
Deep Packet Inspection Through Virtual Platforms using System-On-Chip FPGAs
Submitted by grigby1 on Fri, 07/03/2020 - 12:26pm
resilience
virtual platforms
virtual platform
transaction level modeling
TLM
time-varying systems
time-domain analysis
system-on-chip FPGA
system-on-chip
system on chip
Software
search engines
Scalability
Resiliency
computer architecture
pubcrawl
Mentor Vista
logic design
Inspection
hybrid CPU/FPGA
hardware-IP based architecture
hardware accelerators
Hardware
field programmable gate arrays
ESL
deep packet inspection
CPU-DMA based architecture
