"Parallel secure turbo code for security enhancement in physical layer"
Title | "Parallel secure turbo code for security enhancement in physical layer" |
Publication Type | Conference Paper |
Year of Publication | 2015 |
Authors | A. Motamedi, M. Najafi, N. Erami |
Conference Name | 2015 Signal Processing and Intelligent Systems Conference (SPIS) |
Date Published | Dec |
Publisher | IEEE |
ISBN Number | 978-1-5090-0139-2 |
Accession Number | 15824128 |
Keywords | Bit error rate, buffering latency, channel coding, code words, communication system, concurrent kernel execution, CUDA, Decoding, distribute decoding load, error statistics, general-purpose graphics processing units, GPU, graphics processing units, joint channel-security coding system, memory access improvement, multiple cores, parallel processing, parallel secure turbo code, parallelism, Physical layer, pubcrawl170102, secure decoding algorithm, security, security enhancement, Throughput, Turbo code, turbo codes |
Abstract | Turbo code has been one of the important subjects in coding theory since 1993. This code has low Bit Error Rate (BER) but decoding complexity and delay are big challenges. On the other hand, considering the complexity and delay of separate blocks for coding and encryption, if these processes are combined, the security and reliability of communication system are guaranteed. In this paper a secure decoding algorithm in parallel on General-Purpose Graphics Processing Units (GPGPU) is proposed. This is the first prototype of a fast and parallel Joint Channel-Security Coding (JCSC) system. Despite of encryption process, this algorithm maintains desired BER and increases decoding speed. We considered several techniques for parallelism: (1) distribute decoding load of a code word between multiple cores, (2) simultaneous decoding of several code words, (3) using protection techniques to prevent performance degradation. We also propose two kinds of optimizations to increase the decoding speed: (1) memory access improvement, (2) the use of new GPU properties such as concurrent kernel execution and advanced atomics to compensate buffering latency. |
URL | https://ieeexplore.ieee.org/document/7422336 |
DOI | 10.1109/SPIS.2015.7422336 |
Citation Key | 7422336 |
- joint channel-security coding system
- turbo codes
- Turbo code
- Throughput
- security enhancement
- security
- secure decoding algorithm
- pubcrawl170102
- Physical layer
- parallelism
- parallel secure turbo code
- parallel processing
- multiple cores
- memory access improvement
- Bit error rate
- graphics processing units
- gpu
- general-purpose graphics processing units
- error statistics
- distribute decoding load
- Decoding
- CUDA
- concurrent kernel execution
- communication system
- code words
- channel coding
- buffering latency