Efficient and secure split manufacturing via obfuscated built-in self-authentication
Title | Efficient and secure split manufacturing via obfuscated built-in self-authentication |
Publication Type | Conference Paper |
Year of Publication | 2015 |
Authors | Xiao, K., Forte, D., Tehranipoor, M. M. |
Conference Name | 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) |
Date Published | May 2015 |
Publisher | IEEE |
ISBN Number | 978-1-4673-7421-7 |
Keywords | chip layout, delays, fabrication, Foundries, hardware Trojan insertion, integrated circuit manufacture, integrated circuit reliability, integrated circuits, invasive software, IP piracy, Layout, Logic gates, obfuscated built-in self-authentication, OBISA circuit, pubcrawl170112, reverse engineering, semiconductor supply chain, split manufacturing, Supply chains, trustworthiness, untrusted foundries |
Abstract | The threats of reverse-engineering, IP piracy, and hardware Trojan insertion in the semiconductor supply chain are greater today than ever before. Split manufacturing has emerged as a viable approach to protect integrated circuits (ICs) fabricated in untrusted foundries, but has high cost and/or high performance overhead. Furthermore, split manufacturing cannot fully prevent untargeted hardware Trojan insertions. In this paper, we propose to insert additional functional circuitry called obfuscated built-in self-authentication (OBISA) in the chip layout with split manufacturing process, in order to prevent reverse-engineering and further prevent hardware Trojan insertion. Self-tests are performed to authenticate the trustworthiness of the OBISA circuitry. The OBISA circuit is connected to original design in order to increase the strength of obfuscation, thereby allowing a higher layer split and lower overall cost. Additional fan-outs are created in OBISA circuitry to improve obfuscation without losing testability. Our proposed gating mechanism and net selection method can ensure negligible overhead in terms of area, timing, and dynamic power. Experimental results demonstrate the effectiveness of the proposed technique in several benchmark circuits. |
URL | https://ieeexplore.ieee.org/document/7140229 |
DOI | 10.1109/HST.2015.7140229 |
Citation Key | xiao_efficient_2015 |
- Layout
- untrusted foundries
- trustworthiness
- supply chains
- split manufacturing
- semiconductor supply chain
- reverse engineering
- pubcrawl170112
- OBISA circuit
- obfuscated built-in self-authentication
- Logic gates
- chip layout
- IP piracy
- invasive software
- integrated circuits
- integrated circuit reliability
- integrated circuit manufacture
- hardware Trojan insertion
- Foundries
- fabrication
- delays