Visible to the public Efficient and secure split manufacturing via obfuscated built-in self-authentication

TitleEfficient and secure split manufacturing via obfuscated built-in self-authentication
Publication TypeConference Paper
Year of Publication2015
AuthorsXiao, K., Forte, D., Tehranipoor, M. M.
Conference Name2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)
Date PublishedMay 2015
PublisherIEEE
ISBN Number978-1-4673-7421-7
Keywordschip layout, delays, fabrication, Foundries, hardware Trojan insertion, integrated circuit manufacture, integrated circuit reliability, integrated circuits, invasive software, IP piracy, Layout, Logic gates, obfuscated built-in self-authentication, OBISA circuit, pubcrawl170112, reverse engineering, semiconductor supply chain, split manufacturing, Supply chains, trustworthiness, untrusted foundries
Abstract

The threats of reverse-engineering, IP piracy, and hardware Trojan insertion in the semiconductor supply chain are greater today than ever before. Split manufacturing has emerged as a viable approach to protect integrated circuits (ICs) fabricated in untrusted foundries, but has high cost and/or high performance overhead. Furthermore, split manufacturing cannot fully prevent untargeted hardware Trojan insertions. In this paper, we propose to insert additional functional circuitry called obfuscated built-in self-authentication (OBISA) in the chip layout with split manufacturing process, in order to prevent reverse-engineering and further prevent hardware Trojan insertion. Self-tests are performed to authenticate the trustworthiness of the OBISA circuitry. The OBISA circuit is connected to original design in order to increase the strength of obfuscation, thereby allowing a higher layer split and lower overall cost. Additional fan-outs are created in OBISA circuitry to improve obfuscation without losing testability. Our proposed gating mechanism and net selection method can ensure negligible overhead in terms of area, timing, and dynamic power. Experimental results demonstrate the effectiveness of the proposed technique in several benchmark circuits.

URLhttps://ieeexplore.ieee.org/document/7140229
DOI10.1109/HST.2015.7140229
Citation Keyxiao_efficient_2015