| Title | TTLock: Tenacious and traceless logic locking |
| Publication Type | Conference Paper |
| Year of Publication | 2017 |
| Authors | Yasin, M., Mazumdar, B., Rajendran, J. J. V., Sinanoglu, O. |
| Conference Name | 2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) |
| Keywords | Collaboration, composability, Computer crime, Computer science, Computers, Foundries, industrial property, intellectual property, intellectual property protection technique, Interference, IP piracy, IP piracy revention, logic locking, policy, policy-based governance, pubcrawl, resilience, Resiliency, reverse engineering, TTLock |
| Abstract | Logic locking is an intellectual property (IP) protection technique that prevents IP piracy, reverse engineering and overbuilding attacks by the untrusted foundry or endusers. Existing logic locking techniques are all vulnerable to various attacks, such as sensitization, key-pruning and signal skew analysis enabled removal attacks. In this paper, we propose TTLock that provably withstands all known attacks. TTLock protects a designer-specified number of input patterns, enabling a controlled and provably-secure trade-off between key-pruning attack resilience and removal attack resilience. All the key-bits converge on a single signal, creating maximal interference and thus resisting sensitization attacks. And, obfuscation is performed by modifying the design IP in a secret and traceless way, thwarting signal skew analysis and the removal attack it enables. Experimental results confirm our theoretical expectations that the computational complexity of attacks launched on TTLock grows exponentially with increasing key-size, while the area, power, and delay overhead increases only linearly. |
| DOI | 10.1109/HST.2017.7951830 |
| Citation Key | yasin_ttlock:_2017 |
TTLock: Tenacious and traceless logic locking