| Title | Integrating Compiler Driven Transformation and Simulated Annealing Based Floorplan for Optimized Transient Fault Tolerant DSP Cores |
| Publication Type | Conference Paper |
| Year of Publication | 2018 |
| Authors | Sengupta, Anirban, Kachave, Deepak |
| Conference Name | 2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS) |
| Keywords | battery operated low power, battery operated low power high performance devices, circuit optimisation, compiler driven transformation, compiler security, compositionality, contradictory design goal optimization, delays, digital signal processing chips, DSP core, electronic device realibility, fault security, Fault tolerance, Fault tolerant systems, Finite impulse response filters, high performance devices, integrated circuit layout, integrated circuit reliability, low-power electronics, Metrics, optimized low cost transient fault tolerant DSP core, optimized transient fault tolerant DSP, program compilers, pubcrawl, Resiliency, Scalability, simulated annealing, simulated annealing based floorplan, simulated annealing based optimization process, sub-nanometer technology scale, technology scaling, Transient analysis, Transient fault, transient fault tolerant approach |
| Abstract | Reliability of electronic devices in sub-nanometer technology scale has become a major concern. However, demand for battery operated low power, high performance devices necessitates technology scaling. To meet these contradictory design goals optimization and reliability must be performed simultaneously. This paper proposes by integrating compiler driven transformation and simulated annealing based optimization process for generating optimized low cost transient fault tolerant DSP core. The case study on FIR filter shows improved performance (in terms of reduced area and delay) of proposed approach in comparison to state-of-art transient fault tolerant approach. |
| DOI | 10.1109/iSES.2018.00014 |
| Citation Key | sengupta_integrating_2018 |
Integrating Compiler Driven Transformation and Simulated Annealing Based Floorplan for Optimized Transient Fault Tolerant DSP Cores