| Title | Towards provably-secure performance locking |
| Publication Type | Conference Paper |
| Year of Publication | 2018 |
| Authors | Zaman, M., Sengupta, A., Liu, D., Sinanoglu, O., Makris, Y., Rajendran, J. J. V. |
| Conference Name | 2018 Design, Automation Test in Europe Conference Exhibition (DATE) |
| Keywords | boolean satisfiability (sat), Business, Clocks, composability, Degradation, Electronics packaging, FabScalar, FabScalar microprocessor, functional locking, Integrated circuit modeling, integrated circuit thwarts attacks, intellectual property piracy, IP piracy, multiprocessing systems, performance locking, policy-based governance, power aware computing, provably-secure performance locking, pubcrawl, Resiliency, security, security of data |
| Abstract | Locking the functionality of an integrated circuit (IC) thwarts attacks such as intellectual property (IP) piracy, hardware Trojans, overbuilding, and counterfeiting. Although functional locking has been extensively investigated, locking the performance of an IC has been little explored. In this paper, we develop provably-secure performance locking, where only on applying the correct key the IC shows superior performance; for an incorrect key, the performance of the IC degrades significantly. This leads to a new business model, where the companies can design a single IC capable of different performances for different users. We develop mathematical definitions of security and theoretically, and experimentally prove the security against the state-of-the-art-attacks. We implemented performance locking on a FabScalar microprocessor, achieving a degradation in instructions per clock cycle (IPC) of up to 77% on applying an incorrect key, with an overhead of 0.6%, 0.2%, and 0% for area, power, and delay, respectively. |
| DOI | 10.23919/DATE.2018.8342269 |
| Citation Key | zaman_towards_2018 |
Towards provably-secure performance locking