Visible to the public A Certainty-guaranteed inter/intra-core communication method for multi-core embedded systems

TitleA Certainty-guaranteed inter/intra-core communication method for multi-core embedded systems
Publication TypeConference Paper
Year of Publication2021
AuthorsXuguang, Zhu
Conference Name2021 IEEE International Conference on Power Electronics, Computer Applications (ICPECA)
Date Publishedjan
Keywordscomposability, delays, DSP, Embedded systems, Metrics, multicore computing security, Operating systems, power electronics, Processor scheduling, Program processors, pubcrawl, Real-time Systems, resilience, Resiliency, Scalability, security, software certainty
Abstract

In order to meet the actual needs of operating system localization and high-security operating system, this paper proposes a multi-core embedded high-security operating system inter-core communication mechanism centered on private memory on the core based on the cache mechanism of DSP processors such as Feiteng design. In order to apply it to the multi-core embedded high-security operating system, this paper also combines the priority scheduling scheme used in the design of our actual operating system to analyze the certainty of inter-core communication. The analysis result is: under this communication mechanism There is an upper limit for end-to-end delay, so the certainty of the communication mechanism is guaranteed and can be applied to multi-core high-security embedded operating systems.

DOI10.1109/ICPECA51329.2021.9362570
Citation Keyxuguang_certainty-guaranteed_2021