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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
DSP
biblio
Securing IP Cores in CE Systems using Key-driven Hash-chaining based Steganography
Submitted by grigby1 on Thu, 10/20/2022 - 3:23pm
security
pubcrawl
Metrics
Hardware
Safety
privacy
integrated circuits
composability
Consumer electronics
Steganography
DSP
counterfeiting
digital signal processors
hardware steganography
steganography detection
biblio
A Certainty-guaranteed inter/intra-core communication method for multi-core embedded systems
Submitted by grigby1 on Tue, 02/22/2022 - 12:41pm
power electronics
software certainty
security
Scalability
resilience
real-time systems
pubcrawl
Program processors
Processor scheduling
embedded systems
operating systems
multicore computing security
DSP
delays
Metrics
composability
Resiliency
biblio
Enhanced Functional Obfuscation of DSP core using Flip-Flops and Combinational logic
Submitted by aekwall on Mon, 11/09/2020 - 12:40pm
block logic
Trojan insertion
IP core locking block logic
Intellectual Property cores
Integrated Circuit design flow
ILB
hardware threats
functionally obfuscated design
functional obfuscation based security mechanism
functional obfuscation
flip-flops
flip-flop
DSP design
digital signal processing core
consumer electronics systems
combinational logic
Cryptography
IP core
IC design flow
IP piracy
Consumer electronics
combinational circuits
DSP
logic design
DSP core
digital signal processing chips
industrial property
policy-based governance
composability
pubcrawl
Resiliency
biblio
Hardware Steganography for IP Core Protection of Fault Secured DSP Cores
Submitted by aekwall on Mon, 11/09/2020 - 12:40pm
DSP based IP cores
vendor defined signature
transient fault secured IP cores
signature size
signature free approach
multimedia cores
IP core protection
IP core
high level synthesis
hardware steganography
fault secured DSP cores
Fault secure
entropy value
entropy thresholding
encoding rule
Resiliency
colored interval graph
IP piracy
Steganography
DSP
logic design
digital signal processing chips
Watermarking
industrial property
digital signatures
Entropy
graph theory
policy-based governance
composability
pubcrawl
biblio
Robust Digital Signature to Protect IP Core against Fraudulent Ownership and Cloning
Submitted by grigby1 on Mon, 11/02/2020 - 11:30am
IP cloning
watermarking approach
system-on-chips
system-on-chip
synthesis
robust digital signature
Resiliency
resilience
pubcrawl
Protection.
policy-based governance
multiple security modules
multimedia based reusable Intellectual property cores
IP core
composability
intellectual property security
industrial property
fraudulent ownership
encryption
encoding
DSP
digital signatures
digital signature processing cores
digital signature
digital signal processing chips
Cryptography
crypto digital signature approach
consumer electronic devices
biblio
Effectiveness of the acoustic fingerprint in various acoustical environments
Submitted by aekwall on Mon, 08/03/2020 - 9:15am
Acoustic signal processing
Acoustic Fingerprints
street noise
railway station
musical genres
music
intercepted track
intercepted song
acoustical environments
Resiliency
Acoustic Fingerprint
acoustic disturbances
Acoustic distortion
DSP
composability
pubcrawl
Human behavior
biblio
Does the NIS implementation strategy effectively address cyber security risks in the UK?
Submitted by aekwall on Mon, 02/17/2020 - 1:28pm
NIS directive
cyber spaces
cyber-risk management capabilities
cyber-security risk management capabilities
DSP
IGP
legislation
national framework
NCSC
network and information security
NIS
cyber security risks
NIS framework
NIS implementation
NIS implementation strategy
NIS key strategic objectives
NIS objectives
noncyber elements
OES
Regulation
Smart City
UK Critical National Infrastructure sectors
Standards organizations
security of data
Computer crime
Scalability
cyber security
Resiliency
pubcrawl
Metrics
Supply Chain
risk management
cyber-physical security
IoT
cyber attack
Security Risk Management
CA
CNI
CNI sectors
collaborative implementation approach
connected smart technology implementations
critical national infrastructure
cross-sector CNI service security measures
cyber risk management
biblio
Hermes: Secure heterogeneous multicore architecture design
Submitted by grigby1 on Wed, 02/21/2018 - 12:37pm
Program processors
trust-aware routing algorithm
tenant security
system-on-chip
system-level integration
SoC design
security
secure heterogeneous multicore architecture design
secure cores
Scalability
Resiliency
resilience
pubcrawl
programmable secure router interface
programmable RISC cores
programmable distributed group key management scheme
accelerator function units
nonsecure cores
multiprocessing systems
multiple processing elements
multilevel user-defined security
Multicore processing
multicore computing security
Multicore Computing
Metrics
Hermes architecture
Hardware
general-purpose system-on-chip architectures
DSP
ASIC
application executable code
forum
ODES-11: Deadline Extended
Submitted by brandner on Mon, 12/02/2013 - 8:29am
Calls for Papers
Architectures
Composition
Consumer
Design Automation Tools
Communication
Concurrency and Timing
Embedded Software
Platforms
Control
Defense
Systems Engineering
Energy
Modeling
Wireless Sensing and Actuation
Critical Infrastructure
Real-Time Coordination
Health Care
Resilient Systems
Manufacturing
Science of System Integration
Robotics
Transportation
Validation and Verification
DSP
embedded systems
optimization
Announcement
forum
ODES-11: 11th Workshop on Optimizations for DSP and Embedded Systems
Submitted by brandner on Thu, 10/31/2013 - 4:46am
ODES-11: 11th Workshop on Optimizations for DSP and Embedded Systems
http://odes-workshop.weebly.com/
February 15/16, 2014, Orlando, USA
in conjunction with
IEEE/ACM International Symposium on Code Generation and Optimization (CGO)
http://www.cgo.org/
Calls for Papers
CPS Domains
CPS Technologies
Workshop
optimization
ODES
embedded systems
DSP
Announcement
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