| Title | Security Capsules: An Architecture for Post-Silicon Security Assertion Validation for Systems-on-Chip |
| Publication Type | Conference Paper |
| Year of Publication | 2021 |
| Authors | Raja, Subashree, Bhamidipati, Padmaja, Liu, Xiaobang, Vemuri, Ranga |
| Conference Name | 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
| Date Published | July 2021 |
| Publisher | IEEE |
| ISBN Number | 978-1-6654-3946-6 |
| Keywords | composability, Computer architecture, Dynamic signal selection, dynamic systems, Heuristic algorithms, IP networks, Metrics, Monitoring, network on chip security, post-silicon validation, Program processors, pubcrawl, resilience, Resiliency, Run-time security monitors, Scalability, security, system-on-chip, Trace buffer, Very large scale integration |
| Abstract | In this paper, we propose a methodology for post-silicon validation through the evaluation of security assertions for systems-on-chip (SoC). The methodology is centered around a security architecture in which a "security capsule" is attached to each IP core in the SoC. The security capsule consists of a set of on-line and off-line assertion monitors, a dynamic trace-buffer to trace selected groups of signals, and a dynamic trace controller. The architecture is supported by a trace signal selection and grouping algorithm and a dynamic signal tracing method to evaluate the off-chip monitors. This paper presents the security capsule architecture, the signal selection and grouping algorithm, and the run-time signal tracing method. Results of using the methodology on two SoC architectures based on the OpenRISC-1200 and RISC-V processors are presented. |
| URL | https://ieeexplore.ieee.org/document/9516751 |
| DOI | 10.1109/ISVLSI51109.2021.00053 |
| Citation Key | raja_security_2021 |
Security Capsules: An Architecture for Post-Silicon Security Assertion Validation for Systems-on-Chip