Visible to the public Efficient Acceleration of Decision Tree Algorithms for Encrypted Network Traffic Analysis

TitleEfficient Acceleration of Decision Tree Algorithms for Encrypted Network Traffic Analysis
Publication TypeConference Paper
Year of Publication2021
AuthorsVrána, Roman, Ko\v renek, Jan
Conference Name2021 24th International Symposium on Design and Diagnostics of Electronic Circuits Systems (DDECS)
Date PublishedApril 2021
PublisherIEEE
ISBN Number978-1-6654-3595-6
KeywordsAcceleration, composability, cryptography, Decision Tree, Decision trees, detection, Metrics, Network, network on chip security, Pipelines, pubcrawl, resilience, Resiliency, Scalability, Table lookup, telecommunication traffic, Threat, Vegetation, Wires
AbstractNetwork traffic analysis and deep packet inspection are time-consuming tasks, which current processors can not handle at 100 Gbps speed. Therefore security systems need fast packet processing with hardware acceleration. With the growing of encrypted network traffic, it is necessary to extend Intrusion Detection Systems (IDSes) and other security tools by new detection methods. Security tools started to use classifiers trained by machine learning techniques based on decision trees. Random Forest, Compact Random Forest and AdaBoost provide excellent result in network traffic analysis. Unfortunately, hardware architectures for these machine learning techniques need high utilisation of on-chip memory and logic resources. Therefore we propose several optimisations of highly pipelined architecture for acceleration of machine learning techniques based on decision trees. The optimisations use the various encoding of a feature vector to reduce hardware resources. Due to the proposed optimisations, it was possible to reduce LUTs by 70.5 % for HTTP brute force attack detection and BRAMs by 50 % for application protocol identification. Both with only negligible impact on classifiers' accuracy. Moreover, proposed optimisations reduce wires and multiplexors in the processing pipeline, positively affecting the proposed architecture's maximal achievable frequency.
URLhttps://ieeexplore.ieee.org/document/9417068
DOI10.1109/DDECS52668.2021.9417068
Citation Keyvrana_efficient_2021