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National Science Foundation

Cyber-Physical Systems Virtual Organization

Read-only archive of site from September 29, 2023.

CPS-VO

Hardware Trojan horses (HTH)

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Vivek Venugopalan 

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  • cyber-attack-resilient control techniques
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  • hardware Trojan attack
  • Hardware Trojan horses (HTH)
biblio

Visible to the public Detection of hardware Trojan in SEA using path delay

Submitted by BrandonB on Wed, 05/06/2015 - 11:33am
  • HTH detection and insertion
  • Trojan horses
  • Trojan circuits
  • SEA crypto
  • scalable encryption algorithm crypto
  • Scalable Encryption Algorithm (SEA)
  • payload Trojan detection rate
  • payload Trojan
  • path delay
  • Logic gates
  • logic circuits
  • layout level Trojan insertions
  • IP blocks
  • invasive software
  • Algorithm design and analysis
  • hardware Trojan horses insertion
  • Hardware Trojan horses (HTH)
  • hardware Trojan detection
  • Hardware
  • GDSII hard macros
  • GDSII
  • gate level Trojan insertions
  • fabless design house
  • encryption
  • delays
  • Cryptography
  • ASIC design flow
  • application specific integrated circuits

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