Skip to Main Content Area
CPS-VO
Contact Support
Browse
Calendar
Announcements
Repositories
Groups
Search
Search for Content
Search for a Group
Search for People
Search for a Project
Tagcloud
› Go to login screen
Not a member?
Click here to register!
Forgot username or password?
Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
transistor layout
biblio
Trends on EDA for low power
Submitted by grigby1 on Wed, 03/08/2017 - 1:54pm
state-of-the-art microprocessors
low-power electronics
microprocessor chips
optimization
Physical design
power consumption
Power demand
power optimization
pubcrawl170110
Low power
transistor circuits
transistor layout
transistor network
transistor sizing
Transistors
visualization
visualization tools
AD 2012
Logic gates
Libraries
layout design automation tool
Layout
ISPD Contest
integrated circuit layout
electronic design automation
EDA algorithms
EDA
discrete gate sizing
continuous gate sizing
cell library
Algorithms
Algorithm design and analysis
AD 2013
