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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
low-power electronics
biblio
Modeling Digital Low-Dropout Regulator with a Multiple Sampling Frequency Circuit Technology
Submitted by grigby1 on Fri, 12/11/2020 - 1:42pm
multiple sampling frequency circuit technology
Voltage regulators
Time-frequency Analysis
Time Frequency Analysis
stabilization time
signal conditioning circuits
short setup time
setup time
security
Scalability
sampling frequency circuit model
Resiliency
resilience
Regulators
pubcrawl
circuit setup time
multiple sampling frequencies
model
Metrics
low-power electronics
low supply voltage
low sampling frequency circuit output
Integrated circuit modeling
high sampling frequency circuit
digital low-dropout regulator modeling
digital low-dropout regulator
digital low dropout regulators
digital low drop-out regulators
Circuit stability
biblio
Networks-on-Chip based Deep Neural Networks Accelerators for IoT Edge Devices
Submitted by grigby1 on Fri, 05/15/2020 - 11:45am
low-power electronics
system-on-chip
Space exploration
resource-constrained embedded devices
performance evaluation
On-chip communication
NoC-based deep neural network accelerators
Neurons
neural chips
network-on-chip
network routing
memory size
Memory management
Measurement
massive parallel cores
network on chip security
IoT edge devices
Internet of Things
integrated circuit design
Energy analysis
Design Space Exploration
deep neural network inferences
Deep Neural Network accelerator
circuit optimisation
Artificial Neural Networks
Metrics
Resiliency
resilience
Scalability
biblio
Application Specific Integrated Gate-Drive Circuit for Driving Self-Oscillating Gallium Nitride Logic-Level Power Transistors
Submitted by grigby1 on Fri, 04/24/2020 - 3:08pm
Power transistors
gate-driver functional behaviour
high-speed floating level-shifter
high-voltage transistors
III-V semiconductors
integrated complementary metal-oxide-semiconductor gate-drivers
logic-level power transistors
low-power electronics
MOSFET
package bondwire connections
parallel LC resonant tank
parasitic capacitance
PCB
power density
gate-driver
printed circuit design
prototype printed circuit board design
reset circuitry
Self-oscillating
self-oscillating gallium nitride
self-oscillating gate-drive
switch-mode power supplies
switched mode power supplies
Switching circuits
wide band gap semiconductors
wide bandgap power semiconductors
oscillating behaviors
ASIC
pubcrawl
resilience
Resiliency
privacy
composability
integrated circuit design
Metrics
Resistance
CMOS integrated circuits
Analog integrated circuit
application specific integrated circuits
application specific integrated gate-drive circuit
Logic gates
capacitance 56.7 pF
class-E resonant inverter
CMOS gate-drivers
driver circuits
electrostatic discharge
electrostatic discharge diode
Electrostatic discharges
ESD diode
fabricated gate-driver
gallium compounds
gan
gate drive technologies
biblio
Integrating Compiler Driven Transformation and Simulated Annealing Based Floorplan for Optimized Transient Fault Tolerant DSP Cores
Submitted by aekwall on Mon, 12/02/2019 - 11:07am
simulated annealing
fault security
Finite impulse response filters
high performance devices
integrated circuit layout
integrated circuit reliability
low-power electronics
optimized low cost transient fault tolerant DSP core
optimized transient fault tolerant DSP
electronic device realibility
simulated annealing based floorplan
simulated annealing based optimization process
sub-nanometer technology scale
technology scaling
Transient fault
transient fault tolerant approach
compiler security
program compilers
Resiliency
pubcrawl
Metrics
Transient analysis
delays
fault tolerance
Fault tolerant systems
Compositionality
Scalability
battery operated low power
battery operated low power high performance devices
circuit optimisation
compiler driven transformation
contradictory design goal optimization
digital signal processing chips
DSP core
biblio
Secured Dual-Rail-Precharge Mux-based (DPMUX) symmetric-logic for low voltage applications
Submitted by grigby1 on Mon, 06/11/2018 - 2:48pm
processed data
Metrics
Microelectronics Security
PAA
power analysis attacks
power consumption
Power dissipation
private key cryptography
probability
Probability distribution
low-power electronics
pubcrawl
resilience
Resiliency
secret cryptographic keys
secured dual-rail-precharge mux
side channel attack
Signal to noise ratio
Switches
DPMUX symmetric-logic
average power dissipation
clock cycle
combinatorial logic
composability
cryptographic algorithms
Cryptography
delays
deterministic power
Digital circuits
activity factor
dynamic switching energy
Hardware implementations
Information Leakage
linear relationship
logic circuits
logic design
Logic gates
low voltage applications
biblio
SRAM voltage scaling for energy-efficient convolutional neural networks
Submitted by grigby1 on Thu, 06/07/2018 - 2:06pm
Si
memory power intensive
memory size 8 KByte
Micromechanical devices
neural nets
Neural Network Resilience
pubcrawl
Random access memory
resilience
Resiliency
low-power embedded system
Silicon
silicon-on-insulator
size 28 nm
SRAM chips
SRAM voltage scaling
Training
UTBB FD-SOI CMOS
voltage 310 mV
energy-efficient convolutional neural network
bit error injection
Bit error rate
CMOS memory circuits
ConvNet training
convolutional neural networks
deep learning
electronic engineering computing
elemental semiconductors
energy conservation
approximate SRAM
energy-quality tradeoff
error resiliency
floating-point classification accuracy
Hardware
Hardware Implementation
IoE platform
learning (artificial intelligence)
low-power electronics
biblio
A light-weight hardware/software co-design for pairing-based cryptography with low power and energy consumption
Submitted by grigby1 on Wed, 05/16/2018 - 12:47pm
public key cryptography
Metrics
Montgomery multiplier
multiplying circuits
open-source software PBC implementation
optimal Ate pairing
Pairing based cryptography
pairing-based cryptography
PKC
Power measurement
pubcrawl
low-power electronics
public-key cryptography
Repudiation
resilience
Resiliency
sensors
simple power analysis
Software
system-on-chip
Zynq-7020 SoC
embedded electronic devices
Barreto-Naehrig curves
circuit optimisation
Clocks
composability
cryptographic services
cryptographic system
Cryptography
Differential Power Analysis
ECC
embedded
ARM Cortex A9 processor
energy consumption
field programmable gate arrays
Hardware
hardware-software co-design
hardware-software codesign
Human behavior
human factor
light-weight hardware/software co-design
lightweight devices
biblio
An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics
Submitted by grigby1 on Wed, 02/21/2018 - 12:38pm
secure autonomous aerial surveillance
Multicore Computing
multicore computing security
near-sensor data analytics pipeline
Neural networks
parallel architectures
pubcrawl
regular computing task
remote recognition
resilience
Resiliency
Scalability
Metrics
security of data
seizure detection
sensitive data protection
sensors
size 65 nm
SoC
software programmability
system-on-chip
tightly-coupled multicore cluster
voltage 0.8 V
energy 3.16 pJ
CNN
compute-intensive data processing
computer architecture
computerised instrumentation
Cryptography
data analysis
Data Security
deep convolutional neural network
electroencephalogram
encrypted data collection
encryption
approximate computing
energy conservation
Engines
equivalent reduced instruction set computer operation
Face detection
feature extraction
Fulmine tight power envelope
Internet of Things
Internet-of-Things endpoint
IoT endpoint system-on-chip
low-power electronics
biblio
Trends on EDA for low power
Submitted by grigby1 on Wed, 03/08/2017 - 12:54pm
state-of-the-art microprocessors
low-power electronics
microprocessor chips
optimization
Physical design
power consumption
Power demand
power optimization
pubcrawl170110
Low power
transistor circuits
transistor layout
transistor network
transistor sizing
Transistors
visualization
visualization tools
AD 2012
Logic gates
Libraries
layout design automation tool
Layout
ISPD Contest
integrated circuit layout
electronic design automation
EDA algorithms
EDA
discrete gate sizing
continuous gate sizing
cell library
Algorithms
Algorithm design and analysis
AD 2013
