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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
integrated circuit layout
biblio
Restricting Switching Activity Using Logic Locking to Improve Power Analysis-Based Trojan Detection
Submitted by grigby1 on Wed, 02/26/2020 - 3:38pm
pubcrawl
logic locking method
malicious circuits
million-gate circuits
outsourcing
PCA-based HT detection methods
power analysis-based Trojan detection
power consumption
power consumption analysis
Power demand
principal component analysis
Process Variations
logic locking
resilience
security
semiconductor companies
small sub-circuit collection
supply chain security
Switches
system-on-chip
trojan horse detection
Trojan horses
untrustworthy fabs
hardware Trojan detection
policy-based governance
composability
IP piracy
circuit block extraction
circuit power
cyber physical systems
design for hardware trust
fabrication foundries
gate level
Hardware
Hardware Security
Resiliency
hardware Trojan threat
HT activity
HT power
HT-infected circuits
industrial property
integrated circuit layout
intellectual properties
invasive software
IPS
Logic gates
biblio
Integrating Compiler Driven Transformation and Simulated Annealing Based Floorplan for Optimized Transient Fault Tolerant DSP Cores
Submitted by aekwall on Mon, 12/02/2019 - 11:07am
simulated annealing
fault security
Finite impulse response filters
high performance devices
integrated circuit layout
integrated circuit reliability
low-power electronics
optimized low cost transient fault tolerant DSP core
optimized transient fault tolerant DSP
electronic device realibility
simulated annealing based floorplan
simulated annealing based optimization process
sub-nanometer technology scale
technology scaling
Transient fault
transient fault tolerant approach
compiler security
program compilers
Resiliency
pubcrawl
Metrics
Transient analysis
delays
fault tolerance
Fault tolerant systems
Compositionality
Scalability
battery operated low power
battery operated low power high performance devices
circuit optimisation
compiler driven transformation
contradictory design goal optimization
digital signal processing chips
DSP core
biblio
Trends on EDA for low power
Submitted by grigby1 on Wed, 03/08/2017 - 12:54pm
state-of-the-art microprocessors
low-power electronics
microprocessor chips
optimization
Physical design
power consumption
Power demand
power optimization
pubcrawl170110
Low power
transistor circuits
transistor layout
transistor network
transistor sizing
Transistors
visualization
visualization tools
AD 2012
Logic gates
Libraries
layout design automation tool
Layout
ISPD Contest
integrated circuit layout
electronic design automation
EDA algorithms
EDA
discrete gate sizing
continuous gate sizing
cell library
Algorithms
Algorithm design and analysis
AD 2013
