| Title | A Benchmark Suite of Hardware Trojans for On-Chip Networks |
| Publication Type | Journal Article |
| Year of Publication | 2019 |
| Authors | Wang, Jian, Guo, Shize, Chen, Zhe, Zhang, Tao |
| Journal | IEEE Access |
| Volume | 7 |
| Pagination | 102002—102009 |
| ISSN | 2169-3536 |
| Keywords | benchmark suite, Benchmark testing, benchmarks, cryptography, Functional testing, Hardware, hardware trojan, Hardware Trojans, HT defense methods, information leakage, invasive software, manycore systems, Metrics, multicore systems, multiprocessing systems, network on chip security, network-on-chip, NoC, on-chip networks, performance degradation, resilience, Resiliency, Routing, Scalability, security, side channel analysis, Standards, system-on-chip, Trojan horses |
| Abstract | As recently studied, network-on-chip (NoC) suffers growing threats from hardware trojans (HTs), leading to performance degradation or information leakage when it provides communication service in many/multi-core systems. Therefore, defense techniques against NoC HTs experience rapid development in recent years. However, to the best of our knowledge, there are few standard benchmarks developed for the defense techniques evaluation. To address this issue, in this paper, we design a suite of benchmarks which involves multiple NoCs with different HTs, so that researchers can compare various HT defense methods fairly by making use of them. We first briefly introduce the features of target NoC and its infected modules in our benchmarks, and then, detail the design of our NoC HTs in a one-by-one manner. Finally, we evaluate our benchmarks through extensive simulations and report the circuit cost of NoC HTs in terms of area and power consumption, as well as their effects on NoC performance. Besides, comprehensive experiments, including functional testing and side channel analysis are performed to assess the stealthiness of our HTs. |
| DOI | 10.1109/ACCESS.2019.2929274 |
| Citation Key | wang_benchmark_2019 |
A Benchmark Suite of Hardware Trojans for On-Chip Networks