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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
multiple processing elements
biblio
Hermes: Secure heterogeneous multicore architecture design
Submitted by grigby1 on Wed, 02/21/2018 - 1:37pm
Program processors
trust-aware routing algorithm
tenant security
system-on-chip
system-level integration
SoC design
security
secure heterogeneous multicore architecture design
secure cores
Scalability
Resiliency
resilience
pubcrawl
programmable secure router interface
programmable RISC cores
programmable distributed group key management scheme
accelerator function units
nonsecure cores
multiprocessing systems
multiple processing elements
multilevel user-defined security
Multicore processing
multicore computing security
Multicore Computing
Metrics
Hermes architecture
Hardware
general-purpose system-on-chip architectures
DSP
ASIC
application executable code
