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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
Latches
biblio
Latch-Based Logic Locking
Submitted by aekwall on Mon, 10/04/2021 - 1:53pm
Clocks
delays
Human behavior
Integrated circuit modeling
Latches
Logic gates
pattern locks
propagation delay
pubcrawl
Resiliency
Scalability
security
biblio
Dominance as a New Trusted Computing Primitive for the Internet of Things
Submitted by aekwall on Mon, 12/07/2020 - 12:24pm
resilience
Latches
mainstream IoT devices
neural style transfer
Nucleo-L476RG
operating systems
Predictive Metrics
pubcrawl
Raspberry Pi Compute Module 3
large-scale IoT deployments
Resiliency
Scalability
security of data
sensors
separate service processors
Servers
Trusted Computing
trusted platform modules
geographical area
central entity
CIDER performance overhead
CIDER system
composability
cyber-physical system security
dominant computing paradigms
firmware
firmware image
Authenticated-Watchdog-Timer
Hardware
HummingBoard Edge
Internet of Things
Internet-of-Things
IoT
IoT hardware
IoT platforms
large-scale industrial deployments
biblio
Low-Overhead Robust RTL Signature for DSP Core Protection: New Paradigm for Smart CE Design
Submitted by aekwall on Mon, 11/09/2020 - 1:41pm
low-overhead robust RTL signature
FIR filters
IP piracy
flip-flops
covert signature embedding process
digital signal processor
DSP core protection
DSP-MP IP core
IP vendors
FIR filter
Multimedia Processor
nonsignature FIR RTL design
register-transfer level
reusable Intellectual Property cores
robust IP owner
secured smart CE device
smart CE design
smart Consumer Electronics devices
Registers
Hardware
Resiliency
pubcrawl
composability
policy-based governance
digital signatures
microprocessor chips
Multiplexing
IP networks
digital signal processing chips
Finite impulse response filters
adders
logic circuits
logic design
Latches
Consumer electronics
biblio
A Hierarchical Approach to Self-Timed Circuit Verification
Submitted by aekwall on Mon, 03/16/2020 - 10:39am
asynchronous circuit modeling
timing circuits
self-timed circuit verification
non deterministic behavior
mechanical theorem proving
link-joint style
link joint model
Latches
iterative self-timed circuits
hierarchical verification
hardware description language
greatest common divisor circuit model
greatest common divisor
flip-flops
combinational circuits
asynchronous circuit verification
Resiliency
arbitrated merge
ACL2 theorem prover
Theorem Proving
scalable verification
hardware description languages
Integrated circuit modeling
Wires
Compositionality
Predictive Metrics
Scalability
timing
Logic gates
Iterative methods
Computational modeling
pubcrawl
biblio
Hardware Trojan Insertion and Detection in Asynchronous Circuits
Submitted by grigby1 on Wed, 02/26/2020 - 4:38pm
neural network
Trojan horses
trojan horse detection
Trojan detection methods
synchronous hardware Trojan
supply chain security
Routing
Resiliency
resilience
Random Forest
pubcrawl
Pipelines
asynchronous circuit
logic design
Latches
hardware Trojan threats
hardware Trojan insertion
hardware trojan
Hardware
delays
deep learning
cyber physical systems
asynchronous hardware Trojan circuits
asynchronous circuits
biblio
Classification of Malware programs using autoencoders based deep learning architecture and its application to the microsoft malware Classification challenge (BIG 2015) dataset
Submitted by grigby1 on Wed, 06/20/2018 - 12:56pm
privacy
microcontrollers
Microsoft Malware Classification Challenge BIG2015
microsoft malware Classification challenge dataset
neural network
pattern classification
Pattern recognition
pattern recognition algorithms
principle component analysis
Metrics
pubcrawl
resilience
Resiliency
security
sensors
superior architecture
Time factors
gray scale images
autoencoder
classification process
classifier
Cybersecurity
deep learning
deep learning architecture
Devices
Global Positioning System
Acoustics
Human behavior
invasive software
Latches
learning (artificial intelligence)
malicious programs
malware classification
malware programs
biblio
Trustworthy reconfigurable access to on-chip infrastructure
Submitted by grigby1 on Fri, 02/02/2018 - 1:29pm
security
reconfigurable scan network
reconfigurable scan networks
Registers
Resiliency
RSN
scan pattern generation method
secure DFT
secure pattern retargeting
pubcrawl
security problem
system-on-chip
trustworthiness
trustworthy access pattern generation
trustworthy access sequences
trustworthy data transmission
trustworthy reconfigurable access
Trustworthy Systems
IEEE Std 1500
composability
cyber physical systems
data communication
embedded systems
external interfaces
Hardware Security
IEEE standards
IEEE Std 1149
access mechanisms
IEEE Std 1687
IJTAG
Instruments
integrated circuit testing
JTAG
Latches
Multiplexing
on-chip embedded infrastructure
biblio
Main-Memory Hash Joins on Modern Processor Architectures
Submitted by BrandonB on Wed, 05/06/2015 - 11:55am
Hardware
Instruction sets
Latches
Multicore processing
Probes
tuning
