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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
timing
biblio
The Ideal Block Ciphers - Correlation of AES and PRESENT in Cryptography
Submitted by grigby1 on Wed, 08/18/2021 - 11:15am
PRESENT block cipher
Ultra-light weight
timing
sensors
Scalability
Resiliency
resilience
Registers
pubcrawl
AES cipher
Lightweight Ciphers
IoT
Hardware
encryption
Cryptography
Conferences
Ciphers
Area
biblio
NetCAT: Practical Cache Attacks from the Network
Submitted by grigby1 on Tue, 08/17/2021 - 4:19pm
Human behavior
keystroke analysis
Metrics
microarchitecture
Prefetching
pubcrawl
Random access memory
security
Servers
timing
biblio
ECG-Based Authentication Using Timing-Aware Domain-Specific Architecture
Submitted by aekwall on Wed, 08/11/2021 - 2:54pm
biometric authentication
IoBT Security
side-channel attacks
secure architectures
Internet of Biometric Things (IoBT)
energy efficient
Electrocardiography
Electrocardiogram (ECG)
domain-specific architectures (DSAs)
biometrics (access control)
timing
Resiliency
Scalability
pubcrawl
feature extraction
Internet of Things (IoT)
authentication
computer architecture
Human Factors
biblio
Intrusion Detection System for the MIL-STD-1553 Communication Bus
Submitted by aekwall on Wed, 08/11/2021 - 2:29pm
timing
Intrusion Detection
authentication
Anomaly Detection
machine learning
machine learning algorithms
Vegetation
pubcrawl
Resiliency
composability
intrusion tolerance
communication bus security
markov chain
MIL-STD-1553
Military standards
biblio
Novel Design of Hardware Trojan: A Generic Approach for Defeating Testability Based Detection
Submitted by aekwall on Mon, 06/28/2021 - 12:41pm
Hardware
Support vector machines
Resiliency
pubcrawl
composability
policy-based governance
Trojan horses
timing
Hardware Security
hardware trojan
Controllability
intellectual property
Observability
Stealthy Design.
intellectual property security
biblio
Dependence Analysis and Automated Partitioning for Scalable Formal Analysis of SystemC Designs
Submitted by aekwall on Mon, 05/03/2021 - 1:16pm
Brakes
Compositionality
Hardware
Predictive Metrics
process control
pubcrawl
Resiliency
Scalability
scalable verification
sensors
Software
timing
Wheels
biblio
Time-series Network Anomaly Detection Based on Behaviour Characteristics
Submitted by aekwall on Tue, 04/27/2021 - 1:09pm
Anomaly Detection
time-series
preprocessing
bidirectional gated recurrent unit
abnormal network behaviors detection
belief networks
Deep Belief Network
timing
Logic gates
security
Correlation
Training
component
pubcrawl
Resiliency
cyber-physical systems
Adaptation models
biblio
D-IDS for Cyber-Physical DER Modbus System - Architecture, Modeling, Testbed-based Evaluation
Submitted by grigby1 on Fri, 04/09/2021 - 11:32am
IDS detection accuracy
cyber-physical DER Modbus devices
D-IDS
data-integrity attacks
DER
DER inverters
DER Modbus communication
discrete data points
DoS packets
DoS type attacks
hardware-in-the-loop
hardware-in-the-loop CPS DER
analog data points
IDS detection rate
IEEE 13-bus distribution grid
Modbus-specific IDS rule sets
model-based approach
native clear-text packet
open- source IDS rule syntax formats
physics-based threshold bands
testbed-based evaluation
time 0.25 ms
transaction-based threshold bands
CPS Security
pubcrawl
Resiliency
computer network security
Data models
Computational modeling
Smart Grid
standards
composability
Denial of Service attacks
Protocols
computer architecture
standard protocols
Syntactics
resilience
data integrity
timing
distribution networks
IDS
distributed energy resources
distributed intrusion detection system
Modbus
biblio
A Formal Model for the Automatic Configuration of Access Protection Units in MPSoC-Based Embedded Systems
Submitted by grigby1 on Mon, 03/29/2021 - 11:56am
Resiliency
MPSoC-based embedded systems
multiple processing cores
multiprocessing systems
multiprocessor system-on-chip
on-chip isolation
pubcrawl
real-time systems
resilience
model-based design
Safety
safety-critical embedded system
safety-critical software
security
security-critical embedded system
system-level isolation
system-on-chip
timing
dedicated access protection units
access permissions
access protection
access protection unit
authorisation
Code Generation
composability
configuration code
Data protection
abstract permission declarations
embedded systems
formal model
Hardware
heterogeneous system-on-chip platforms
information flow requirements
information flow tracking
internal communication links
Metrics
biblio
Hardware Design of Polynomial Multiplication for Byte-Level Ring-LWE Based Cryptosystem
Submitted by aekwall on Mon, 03/15/2021 - 12:10pm
NIST PQC Standardization Process
BRAMs
byte-level modulus
byte-level ring-LWE based cryptosystem
computational time-consuming block
DSPs
high-level synthesis based hardware design methodology
ideal lattice
LAC
multiplication core
high level synthesis
polynomial multiplication
ring learning with error problem
ring LWE
time 4.3985 ns
time 5.052 ns
time 5.133 ns
Vivado HLS compiler
Xilinx Artix-7 family FPGA
NIST
Scalability
lattice-based cryptography
Cryptography
Hardware
Table lookup
learning (artificial intelligence)
Resiliency
pubcrawl
Metrics
field programmable gate arrays
post quantum cryptography
timing
polynomials
Software algorithms
Compositionality
program compilers
compiler security
logic design
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