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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
link-joint style
biblio
A Hierarchical Approach to Self-Timed Circuit Verification
Submitted by aekwall on Mon, 03/16/2020 - 10:39am
asynchronous circuit modeling
timing circuits
self-timed circuit verification
non deterministic behavior
mechanical theorem proving
link-joint style
link joint model
Latches
iterative self-timed circuits
hierarchical verification
hardware description language
greatest common divisor circuit model
greatest common divisor
flip-flops
combinational circuits
asynchronous circuit verification
Resiliency
arbitrated merge
ACL2 theorem prover
Theorem Proving
scalable verification
hardware description languages
Integrated circuit modeling
Wires
Compositionality
Predictive Metrics
Scalability
timing
Logic gates
Iterative methods
Computational modeling
pubcrawl
