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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
combinational circuits
biblio
Enhanced Functional Obfuscation of DSP core using Flip-Flops and Combinational logic
Submitted by aekwall on Mon, 11/09/2020 - 1:40pm
block logic
Trojan insertion
IP core locking block logic
Intellectual Property cores
Integrated Circuit design flow
ILB
hardware threats
functionally obfuscated design
functional obfuscation based security mechanism
functional obfuscation
flip-flops
flip-flop
DSP design
digital signal processing core
consumer electronics systems
combinational logic
Cryptography
IP core
IC design flow
IP piracy
Consumer electronics
combinational circuits
DSP
logic design
DSP core
digital signal processing chips
industrial property
policy-based governance
composability
pubcrawl
Resiliency
biblio
Mystic: Mystifying IP Cores Using an Always-ON FSM Obfuscation Method
Submitted by aekwall on Mon, 11/09/2020 - 1:32pm
integrated circuit industry
IP piracy
application specific integrated circuits
ASIC technology
circuit complexity
combinational circuits
finite state machine
FSM obfuscation method
hardware obfuscation method
Hardware Security
IP overproduction
ITC99 circuit benchmarks
logic encryption
Logic masking
Mystic obfuscation approach
Mystic protection method
mystifying IP cores
Logic gates
Hardware
Resiliency
pubcrawl
composability
policy-based governance
Production
Complexity theory
microprocessor chips
IP networks
obfuscation
reverse engineering
encoding
finite state machines
logic circuits
logic design
size 45.0 nm
biblio
Automated Synthesis of Differential Power Attack Resistant Integrated Circuits
Submitted by aekwall on Mon, 08/24/2020 - 12:41pm
Dynamic Differential Logic
cryptographic processors
cryptographic systems
differential circuit design
differential logic
Differential Power Analysis
differential power analysis attacks
differential power attack resistant integrated circuits
DPA attack resistance
DPA resistant cell designs
combinational cells
fully automated synthesis system DPA resistant integrated circuits
MDPL
multiplying circuits
RT level Verilog specifications
secret key information
Secure Differential Multiplexer Logic
sequential cells
sequential circuits
power consumption
Resiliency
pubcrawl
composability
Cryptography
standards
tools
Libraries
Automated Response Actions
Logic gates
private key cryptography
Power demand
logic design
Hardware Security
Resistance
combinational circuits
Automated Synthesis
CMOS logic circuits
CMOS synthesis
biblio
A Hierarchical Approach to Self-Timed Circuit Verification
Submitted by aekwall on Mon, 03/16/2020 - 10:39am
asynchronous circuit modeling
timing circuits
self-timed circuit verification
non deterministic behavior
mechanical theorem proving
link-joint style
link joint model
Latches
iterative self-timed circuits
hierarchical verification
hardware description language
greatest common divisor circuit model
greatest common divisor
flip-flops
combinational circuits
asynchronous circuit verification
Resiliency
arbitrated merge
ACL2 theorem prover
Theorem Proving
scalable verification
hardware description languages
Integrated circuit modeling
Wires
Compositionality
Predictive Metrics
Scalability
timing
Logic gates
Iterative methods
Computational modeling
pubcrawl
biblio
Combinational Hardware Trojan Detection Using Logic Implications
Submitted by grigby1 on Wed, 04/11/2018 - 3:00pm
logical implications
valid logic implications
Trojan horses
trojan horse detection
security
Resiliency
resilience
pubcrawl
proof-of-concept demonstration
potential benefit
Payloads
combinational circuits
logic simulation
Logic gates
logic design
invasive software
Integrated circuit modeling
Hardware
cyber physical systems
composability
combinational hardware trojan detection
biblio
Evolving side-channel resistant reconfigurable hardware for elliptic curve cryptography
Submitted by grigby1 on Tue, 12/12/2017 - 1:25pm
Metrics
Xilinx Kintex-7 FPGA
timing attacks
side-channel resistant reconfigurable hardware
side-channel attacks
security-level
Scalability
Resiliency
reconfigurable hardware design
public-key cryptosystems
public key cryptography
pubcrawl
propagation delay minimization
power analysis attacks
noninvasive side channel attacks
minimisation
Algorithm design and analysis
Hardware
genetic algorithms
genetic algorithm
fitness function
field programmable gate arrays
Evolutionary algorithm
Elliptic curves
elliptic curve discrete logarithm
Elliptic curve cryptography
elliptic curve cryptographic hardware
elliptic curve cryptographic combinational logic circuits
Cryptographic Protocols
cryptographic applications
combinational circuits
circuit size minimization
