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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
Clocks
biblio
High Speed Parallel RC4 Key Searching Brute Force Attack Based on FPGA
Submitted by grigby1 on Fri, 09/04/2020 - 3:36pm
Hardware
Xilinx XC3S1600E-4 FPGA device
stream cipher
RC4 algorithm
RC4
random-access storage
pubcrawl
process control
policy-based governance
on-chip BRAM
main controller
key searching unit
key searching speed
Human Factors
High Speed Parallel RC4 Key Searching Brute Force Attack
block RAM
frequency 128 MHz
FPGA
forecast keying methods
Force
field programmable gate arrays
field programmable gate array
encryption
Cryptography
Clocks
clock rate
Ciphers
brute force attacks
Brute force
biblio
Real-Time SCADA Attack Detection by Means of Formal Methods
Submitted by aekwall on Mon, 03/16/2020 - 10:29am
critical machines
Chemicals
programmable controllers
programmable logic controller
Clocks
formal methods
chemical manufacturing plants
chemical substances
control smart grid
Compositionality
real-time SCADA attack detection
SCADA control systems
SCADA water distribution system
timed automata
timed automaton
timed temporal logic
water supply
security
Semantics
SCADA Systems Security
automata theory
automata
Safety
Temporal Logic
model checking
pubcrawl
Human behavior
Resiliency
SCADA systems
SCADA
critical infrastructures
critical infrastructure
security of data
biblio
Hybrid Logical Clocks for Database Forensics: Filling the Gap between Chain of Custody and Database Auditing
Submitted by aekwall on Mon, 03/09/2020 - 11:05am
Database Security
causality
centralised vector-clock architecture
chain of custody
chain of custody properties
CoC properties
commercial database systems
database audit
database audit records
auditing capabilities
digital evidence
forensically-aware distributed database architecture
hybrid logical clocks
role segregation
third-party verification
transactional databases
user transactions
Security Audits
Provenance
computer architecture
Resiliency
Human behavior
pubcrawl
Distributed databases
Forensics
Digital Forensics
Data mining
security
Proposals
database forensics
database management systems
Scalability
Clocks
auditing
action accountability
admissible audit records
biblio
Time-Related Hardware Trojan Attacks on Processor Cores
Submitted by grigby1 on Wed, 02/26/2020 - 4:39pm
real-time clock
Trojan horses
trojan horse detection
trigger conditions
time-related Hardware Trojan attacks
time information
system power-on
supply chain security
specific time period passes
specific realworld time
RISC-V processor
Resiliency
resilience
relative-time based Trojan
real-time systems
real-time clock circuits
Clocks
Random access memory
pubcrawl
Payloads
modern electronic systems
microprocessor chips
Kernel
invasive software
internal information
Hardware Trojan designs
hardware trojan
Hardware
extra power consumption
design security
cyber physical systems
biblio
White-Box Atomic Multicast
Submitted by grigby1 on Tue, 02/18/2020 - 11:53am
genuine atomic multicast protocol
white-box optimisations
white-box atomic multicast
white box cryptography
Resiliency
resilience
replication
pubcrawl
optimisation
multicast protocols
Metrics
message delays
Atomic multicast
Fault tolerant systems
fault tolerance
destination processes
destination groups
delays
Concurrency
composability
Clocks
classical Skeen's multicast protocol
atomic multicast needs
biblio
A high-throughput fully digit-serial polynomial basis finite field \$\textbackslashtextGF(2ˆm)\$ multiplier for IoT applications
Submitted by aekwall on Mon, 01/20/2020 - 11:49am
Clocks
computer architecture
digit-level architecture
Elliptic curve cryptography
exponentiation
finite field arithmetic
Hardware
Internet of Things
pubcrawl
redundant basis
Resiliency
Scalability
wireless sensor networks
biblio
Reconfigurable Architecture to Speed-up Modular Exponentiation
Submitted by grigby1 on Mon, 12/30/2019 - 2:18pm
modular exponentiation
Xilinx Virtex 7 FPGA
Scalability
RSA protocols
Resiliency
reconfigurable architectures
Reconfigurable Architecture
random number generation
Random access memory
public key cryptography
pubcrawl
pseudorandom number generator
Pre-computation techniques
Modular Multiplication
batch multiplication
hardware architecture
Hardware
frequency 200.0 MHz
FPGA
field programmable gate arrays
exponentiation
digital arithmetic
Diffie-Hellman like protocols
Diffie-Hellman key pair
Cryptography
computer architecture
computationally intensive cryptographic operations
Clocks
biblio
Architecture Analysis and Verification of I3C Protocol
Submitted by grigby1 on Tue, 11/12/2019 - 4:29pm
SoC
MIPI
Monitoring
Pins
policy-based governance
privacy
protocol verification
Protocols
pubcrawl
IP networks
system Verilog
test environments
Universal Verification Methodology
UVM
verification components
verification environment
VLSI
formal verification
back end design
base class library
Clocks
collaboration
composability
Compositionality
Conferences
digital integrated circuits
Aerospace electronics
front end design
hardware description languages
I3C
I3C bus protocol
improved inter integrated circuit
integrated circuit design
integrated circuit testing
biblio
Formal Verification Technology for Asynchronous Communication Protocol
Submitted by grigby1 on Tue, 11/12/2019 - 4:29pm
policy-based governance
verification work efficiency
UART communication
traditional simulation method
Software
pubcrawl
PSL
Protocols
protocol verification
property
product design quality
Product design
process control
privacy
aerospace FPGA software products
formal verification technology
formal verification
field programmable gate arrays
Compositionality
composability
complete verification process
collaboration
Clocks
blind spots
asynchronous communication protocol
asynchronous communication
assert
biblio
Design of Generic Verification Procedure for IIC Protocol in UVM
Submitted by grigby1 on Tue, 11/12/2019 - 4:29pm
SDA(Serial data line)
Monitoring
policy-based governance
privacy
product development
program verification
protocol verification
Protocols
pubcrawl
SCL(Serial clock line)
Mentor graphic Questasim 10.4e
standard method
Synchronization
Universal Verification Methodology
UVC(Universal verification component)
UVM
UVM(Univeral verification methodology)
Verilog
Vivado
field buses
APB(Advanced peripheral bus)
bugs
Clocks
code coverage
collaboration
composability
Compositionality
Conferences
DUT(Design under test)
Aerospace electronics
functional coverage
generic verification procedure
hardware description languages
Hardware design languages
IIC bus protocol
IIC controller
IIC protocol
Libraries
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