Visible to the public Design of a Chaotic Oscillator based Model Building Attack Resistant Arbiter PUF

TitleDesign of a Chaotic Oscillator based Model Building Attack Resistant Arbiter PUF
Publication TypeConference Paper
Year of Publication2019
AuthorsBalijabudda, Venkata Sreekanth, Thapar, Dhruv, Santikellur, Pranesh, Chakraborty, Rajat Subhra, Chakrabarti, Indrajit
Conference Name2019 Asian Hardware Oriented Security and Trust Symposium (AsianHOST)
PublisherIEEE
ISBN Number978-1-7281-3544-1
Keywordsarbiter PUF, chaos, chaotic behaviour, chaotic oscillator, Chua's Oscillator, Chua's oscillator circuit, composability, conventional machine learning, cryptography, field programmable gate arrays, FPGA, Integrated circuit modeling, learning (artificial intelligence), Mathematical model, Measurement, Metrics, Modeling Attacks, Monte Carlo analysis, Monte Carlo methods, oscillating behaviors, oscillating systems, Oscillators, physical unclonable functions, privacy, pubcrawl, PUF, PUF architecture, resilience, Resiliency, Resistance, security, security of data, Unclonability
Abstract

Physical Unclonable Functions (PUFs) are vulnerable to various modelling attacks. The chaotic behaviour of oscillating systems can be leveraged to improve their security against these attacks. We have integrated an Arbiter PUF implemented on a FPGA with Chua's oscillator circuit to obtain robust final responses. These responses are tested against conventional Machine Learning and Deep Learning attacks for verifying security of the design. It has been found that such a design is robust with prediction accuracy of nearly 50%. Moreover, the quality of the PUF architecture is evaluated for uniformity and uniqueness metrics and Monte Carlo analysis at varying temperatures is performed for determining reliability.

URLhttps://ieeexplore.ieee.org/document/9006686
DOIhttps://ieeexplore.ieee.org/document/9006686
Citation Keybalijabudda_design_2019