| Title | Nested Pipeline Hardware Self-Organizing Map for High Dimensional Vectors |
| Publication Type | Conference Paper |
| Year of Publication | 2020 |
| Authors | Hikawa, H. |
| Conference Name | 2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) |
| Keywords | Clocks, clustering, compositionality, Computer architecture, expandability, field programmable gate arrays, FPGA, frequency 60.0 MHz, fully parallel computation, Hardware, high dimensional vectors, homogeneous modular structure, low-dimensional vectors, MNIST, multiple clocks, nested architecture, nested pipeline hardware self-organizing map, neural chips, neural net architecture, Neurons, operable clock frequency, original nested SOM, pipeline computation, pipeline processing, Pipelines, pubcrawl, Resiliency, self-organising feature maps, Self-organizing feature maps, Self-Organizing Map, sequential computation, single vector, Vectors, VHDL, weight vector update |
| Abstract | This paper proposes a hardware Self-Organizing Map (SOM) for high dimensional vectors. The proposed SOM is based on nested architecture with pipeline processing. Due to homogeneous modular structure, the nested architecture provides high expandability. The original nested SOM was designed to handle low-dimensional vectors with fully parallel computation, and it yielded very high performance. In this paper, the architecture is extended to handle much higher dimensional vectors by using sequential computation, which requires multiple clocks to process a single vector. To increase the performance, the proposed architecture employs pipeline computation, in which search of winner neuron and weight vector update are carried out simultaneously. Operable clock frequency for the system was 60 MHz, and its throughput reached 15012 million connection updates per second (MCUPS). |
| DOI | 10.1109/ICECS49266.2020.9294973 |
| Citation Key | hikawa_nested_2020 |
Nested Pipeline Hardware Self-Organizing Map for High Dimensional Vectors