| Title | Design Obfuscation versus Test |
| Publication Type | Conference Paper |
| Year of Publication | 2020 |
| Authors | Farahmandi, Farimah, Sinanoglu, Ozgur, Blanton, Ronald, Pagliarini, Samuel |
| Conference Name | 2020 IEEE European Test Symposium (ETS) |
| Keywords | automatic test pattern generation, high level synthesis, Human Behavior, integrated circuit design, logic locking, logic obfuscation, pattern locks, pubcrawl, Resiliency, Scalability, test |
| Abstract | The current state of the integrated circuit (IC) ecosystem is that only a handful of foundries are at the forefront, continuously pushing the state of the art in transistor miniaturization. Establishing and maintaining a FinFET-capable foundry is a billion dollar endeavor. This scenario dictates that many companies and governments have to develop their systems and products by relying on 3rd party IC fabrication. The major caveat within this practice is that the procured silicon cannot be blindly trusted: a malicious foundry can effectively modify the layout of the IC, reverse engineer its IPs, and overproduce the entire chip. The Hardware Security community has proposed many countermeasures to these threats. Notably, obfuscation has gained a lot of traction - here, the intent is to hide the functionality from the untrusted foundry such that the aforementioned threats are hindered or mitigated. In this paper, we summarize the research efforts of three independent research groups towards achieving trustworthy ICs, even when fabricated in untrusted offshore foundries. We extensively address the use of logic locking and its many variants, as well as the use of high-level synthesis (HLS) as an obfuscation approach of its own. |
| DOI | 10.1109/ETS48528.2020.9131590 |
| Citation Key | farahmandi_design_2020 |
Design Obfuscation versus Test