| Title | Efficient Modeling of HIL Multi-Grid System for Scalability Concurrency in CPS Security Testbed |
| Publication Type | Conference Paper |
| Year of Publication | 2019 |
| Authors | Ravikumar, Gelli, Hyder, Burhan, Govindarasu, Manimaran |
| Conference Name | 2019 North American Power Symposium (NAPS) |
| Keywords | 100% realtime performance, composability, Computational modeling, Concurrency, Concurrent computing, coordinated cyber attacks, CPS, cyber physical systems, cyber-event-triggered power grid blackout, cyber-event-triggered power system blackout, cyber-physical system testbeds, Cyber-physical systems, grid data streams, Hardware-in-the-Loop, hardware-in-the-loop CPS security testbeds, HIL CPS security testbed, HIL multigrid system, HIL realtime digital simulator environment, IEC standards, IEEE standards, IEEE-118 bus grid model, IEEE-39 bus grid models, industry-grade hardware, interdependent events, large-scale grid models, Metrics, modular integration designs, Multi-Grid, multigrid isolated models, multitude designs, phasor measurement, phasor measurement units, physics-constrained recovery, Power and Cyber System Testbed, power engineering computing, power grids, real-time execution environment, Real-time Systems, Relays, resilience, Resiliency, restoration process, SCADA, Scalability, security, security of data, Software systems, synthetic grid model, Ukrainian grid, WAMS |
| Abstract | Cyber-event-triggered power grid blackout compels utility operators to intensify cyber-aware and physics-constrained recovery and restoration process. Recently, coordinated cyber attacks on the Ukrainian grid witnessed such a cyber-event-triggered power system blackout. Various cyber-physical system (CPS) testbeds have attempted with multitude designs to analyze such interdependent events and evaluate remedy measures. However, resource constraints and modular integration designs have been significant barriers while modeling large-scale grid models (scalability) and multi-grid isolated models (concurrency) under a single real-time execution environment for the hardware-in-the-loop (HIL) CPS security testbeds. This paper proposes a meticulous design and effective modeling for simulating large-scale grid models and multi-grid isolated models in a HIL realtime digital simulator environment integrated with industry-grade hardware and software systems. We have used our existing HIL CPS security testbed to demonstrate scalability by the realtime performance of a Texas-2000 bus US synthetic grid model and concurrency by the real-time performance of simultaneous ten IEEE-39 bus grid models and an IEEE-118 bus grid model. The experiments demonstrated significant results by 100% realtime performance with zero overruns, low latency while receiving and executing control signals from SEL Relays via IEC-61850 protocol and low latency while computing and transmitting grid data streams including stability measures via IEEE C37.118 synchrophasor data protocol to SEL Phasor Data Concentrators. |
| DOI | 10.1109/NAPS46351.2019.9000259 |
| Citation Key | ravikumar_efficient_2019 |
Efficient Modeling of HIL Multi-Grid System for Scalability Concurrency in CPS Security Testbed