| Title | Efficient Reed-Muller Implementation for Fuzzy Extractor Schemes |
| Publication Type | Conference Paper |
| Year of Publication | 2019 |
| Authors | Barbareschi, M., Barone, S., Mazzeo, A., Mazzocca, N. |
| Conference Name | 2019 14th International Conference on Design Technology of Integrated Systems In Nanoscale Era (DTIS) |
| Date Published | apr |
| Keywords | area constraints, attack models, counterfeiting, cryptography, Decoding, delay constraints, distributed applications, efficient Reed-Muller implementation, electronic devices, error correction codes, field programmable gate arrays, FPGA, Fuzzy Cryptography, fuzzy extraction scheme, fuzzy extractor schemes, fuzzy set theory, fuzzy-extractor, Hamming distance, immunity, Internet-of-Things, intrinsic hardware security, medium-range FPGA device, Metrics, physical tampering, physical unclonable functions, pubcrawl, PUF, PUF circuits, PUF implementations, Reed-Muller, Reed-Muller codes, Reed-Muller ECC design, Resiliency, responses stability, Scalability, security, security problem, Table lookup |
| Abstract | Nowadays, physical tampering and counterfeiting of electronic devices are still an important security problem and have a great impact on large-scale and distributed applications, such as Internet-of-Things. Physical Unclonable Functions (PUFs) have the potential to be a fundamental means to guarantee intrinsic hardware security, since they promise immunity against most of known attack models. However, inner nature of PUF circuits hinders a wider adoption since responses turn out to be noisy and not stable during time. To overcome this issue, most of PUF implementations require a fuzzy extraction scheme, able to recover responses stability by exploiting error correction codes (ECCs). In this paper, we propose a Reed-Muller (RM) ECC design, meant to be embedded into a fuzzy extractor, that can be efficiently configured in terms of area/delay constraints in order to get reliable responses from PUFs. We provide implementation details and experimental evidences of area/delay efficiency through syntheses on medium-range FPGA device. |
| DOI | 10.1109/DTIS.2019.8735029 |
| Citation Key | barbareschi_efficient_2019 |
Efficient Reed-Muller Implementation for Fuzzy Extractor Schemes