| Title | Invariance Checking Based Trojan Detection Method for Three-Dimensional Integrated Circuits |
| Publication Type | Conference Paper |
| Year of Publication | 2020 |
| Authors | Zhang, Zhiming, Yu, Qiaoyan |
| Conference Name | 2020 IEEE International Symposium on Circuits and Systems (ISCAS) |
| Date Published | oct |
| Keywords | Hardware, Metrics, network on chip security, pubcrawl, Resiliency, Routing, Scalability, Three-dimensional displays, Through-silicon vias, Trojan horses, Two dimensional displays |
| Abstract | Recently literature indicates that stack based three-dimensional (3D) integration techniques may bring in new security vulnerabilities, such as new attack surfaces for hardware Trojan (HT) insertion. Compared to its two-dimensional counterpart (2DHTs), a 3D hardware Trojan (3DHT) could be stealthily distributed in multiple tiers in a single 3D chip. Although the comprehensive models for 3DHTs are available in recent work, there still lacks 3DHT detection and mitigation methods, especially run-time countermeasures against 3DHTs. This work proposes to leverage the 3D communication infrastructure, 3D network-on-chips (NoCs), to tackle the cross-tier hardware Trojans in stacked multi-tier chips. An invariance checking method is further proposed to detect the Trojans that induce malicious NoC packets or facilitate information leak. The proposed method is successfully deployed in NoC routers and achieves a Trojan detection rate of over 94%. The synthesis result of a hardened router at a 45nm technology node shows that the proposed invariance checking only increases the area by 6.49% and consumes 3.76% more dynamic power than an existing 3D router. The NoC protected with the proposed method is applied to the image authentication in a 3D system. The case study indicates that the proposed security measure reduces the correlation coefficient by up to 31% over the baseline. |
| DOI | 10.1109/ISCAS45731.2020.9180583 |
| Citation Key | zhang_invariance_2020 |
Invariance Checking Based Trojan Detection Method for Three-Dimensional Integrated Circuits