| Title | Securing IP Cores in CE Systems using Key-driven Hash-chaining based Steganography |
| Publication Type | Conference Paper |
| Year of Publication | 2020 |
| Authors | Rathor, Mahendra, Sarkar, Pallabi, Mishra, Vipul Kumar, Sengupta, Anirban |
| Conference Name | 2020 IEEE 10th International Conference on Consumer Electronics (ICCE-Berlin) |
| Date Published | nov |
| Keywords | composability, Consumer electronics, counterfeiting, digital signal processors, DSP, Hardware, hardware steganography, integrated circuits, Metrics, privacy, pubcrawl, Safety, security, steganography, steganography detection |
| Abstract | Digital signal processor (DSP) intellectual property (IP) cores are the underlying hardware responsible for high performance data intensive applications. However an unauthorized IP vendor may counterfeit the DSP IPs and infuse them into the design-chain. Thus fake IPs or integrated circuits (ICs) are unknowingly integrated into consumer electronics (CE) systems, leading to reliability and safety issues for users. The latent solution to this threat is hardware steganography wherein vendor's secret information is covertly inserted into the design to enable detection of counterfeiting. A key-regulated hash-modules chaining based IP steganography is presented in our paper to secure against counterfeiting threat. The proposed approach yielded a robust steganography achieving very high security with regard to stego-key length than previous approaches. |
| DOI | 10.1109/ICCE-Berlin50680.2020.9352192 |
| Citation Key | rathor_securing_2020 |
Securing IP Cores in CE Systems using Key-driven Hash-chaining based Steganography