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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
integrated circuit modelling
biblio
A PUF-Based Data-Device Hash for Tampered Image Detection and Source Camera Identification
Submitted by grigby1 on Thu, 04/08/2021 - 5:12pm
invariant image features
Camera Identification
CASIA database
CMOS image sensor-based PUF
CMOS image sensors
digital content creation
digital image forensics
forgery content detection
geometric transformations
image acquisition timestamp
image hash
image processing operations
image tampering problems
Bernoulli random space
perceptual data-device hash
Perceptual Image Hash
PUF-based data-device hash
size 180.0 nm
source camera identification
standard content-preserving manipulations
tamper-resistant random PUF response
tampered image detection
TSMC technology
video footage
video watermarking
object detection
Digital Forensics
pubcrawl
Human behavior
Metrics
resilience
Resiliency
Scalability
Forensics
Cameras
digital devices
Image forensics
information forensics
feature extraction
image watermarking
Watermarking
copy protection
Physical Unclonable Function
digital images
integrated circuit modelling
video coding
image capture
Forgery
acquisition device identification
benign content
biblio
Design-Based Fingerprinting Using Side-Channel Power Analysis for Protection Against IC Piracy
Submitted by grigby1 on Thu, 07/30/2020 - 2:06pm
machine learning methods
integrated circuit modelling
integrated circuit testing
integrated circuits
Inverters
ip protection
IP/IC providers
learning (artificial intelligence)
Logic gates
machine learning
Integrated circuit modeling
Metrics
minimal design variations
modified netlist
pubcrawl
resilience
side-channel power analysis
supply chains
Trojan horses
fingerprinting scheme
policy-based governance
composability
IP piracy
Benchmark testing
circuit CAD
Computer crime
Cryptography
design-based fingerprinting
Fingerprinting
Resiliency
gate-level netlist changes
Hardware
Human behavior
Human Factors
IC design flow
IC piracy
industrial property
integrated circuit design
biblio
Accurate Diagnosis of Interconnect Open Defects Based on the Robust Enhanced Aggressor Victim Model
Submitted by grigby1 on Wed, 12/20/2017 - 8:51pm
Logic gates
unknown values
test generation
SMT
Robustness
robust enhanced aggressor victim model
Resiliency
pubcrawl
privacy
physical failure analysis
oscillating behaviors
open faults
nanotechnology
nanoscale technologies
Metrics
ATPG
Interconnect opens
interconnect open defects
integrated circuit modelling
Integrated circuit modeling
Integrated circuit interconnections
failure analysis
electrical parameters
diagnostic classification algorithm
diagnose
Couplings
composability
Circuit faults
Capacitance
automatic test pattern generation
