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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
ATPG
biblio
Is Robust Design-for-Security Robust Enough? Attack on Locked Circuits with Restricted Scan Chain Access
Submitted by aekwall on Tue, 09/08/2020 - 8:59am
locked circuits
Chained Attacks
working chip
unauthorized scan access
secret key recovery
scan chain
SAT attack
robust DFS technique
robust DFS design
robust design-for-security architecture
restricted scan chain access
logic locking security
logic locking attacks
Scalability
IP piracy
Boolean satisfiability based attack
benchmark circuits
ATPG
Boolean functions
logic circuits
computability
Security analysis
logic locking
pubcrawl
Resiliency
Cryptography
biblio
Accurate Diagnosis of Interconnect Open Defects Based on the Robust Enhanced Aggressor Victim Model
Submitted by grigby1 on Wed, 12/20/2017 - 7:51pm
Logic gates
unknown values
test generation
SMT
Robustness
robust enhanced aggressor victim model
Resiliency
pubcrawl
privacy
physical failure analysis
oscillating behaviors
open faults
nanotechnology
nanoscale technologies
Metrics
ATPG
Interconnect opens
interconnect open defects
integrated circuit modelling
Integrated circuit modeling
Integrated circuit interconnections
failure analysis
electrical parameters
diagnostic classification algorithm
diagnose
Couplings
composability
Circuit faults
Capacitance
automatic test pattern generation
