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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
circuit optimisation
biblio
Networks-on-Chip based Deep Neural Networks Accelerators for IoT Edge Devices
Submitted by grigby1 on Fri, 05/15/2020 - 12:45pm
low-power electronics
system-on-chip
Space exploration
resource-constrained embedded devices
performance evaluation
On-chip communication
NoC-based deep neural network accelerators
Neurons
neural chips
network-on-chip
network routing
memory size
Memory management
Measurement
massive parallel cores
network on chip security
IoT edge devices
Internet of Things
integrated circuit design
Energy analysis
Design Space Exploration
deep neural network inferences
Deep Neural Network accelerator
circuit optimisation
Artificial Neural Networks
Metrics
Resiliency
resilience
Scalability
biblio
Integrating Compiler Driven Transformation and Simulated Annealing Based Floorplan for Optimized Transient Fault Tolerant DSP Cores
Submitted by aekwall on Mon, 12/02/2019 - 12:07pm
simulated annealing
fault security
Finite impulse response filters
high performance devices
integrated circuit layout
integrated circuit reliability
low-power electronics
optimized low cost transient fault tolerant DSP core
optimized transient fault tolerant DSP
electronic device realibility
simulated annealing based floorplan
simulated annealing based optimization process
sub-nanometer technology scale
technology scaling
Transient fault
transient fault tolerant approach
compiler security
program compilers
Resiliency
pubcrawl
Metrics
Transient analysis
delays
fault tolerance
Fault tolerant systems
Compositionality
Scalability
battery operated low power
battery operated low power high performance devices
circuit optimisation
compiler driven transformation
contradictory design goal optimization
digital signal processing chips
DSP core
biblio
A light-weight hardware/software co-design for pairing-based cryptography with low power and energy consumption
Submitted by grigby1 on Wed, 05/16/2018 - 1:47pm
public key cryptography
Metrics
Montgomery multiplier
multiplying circuits
open-source software PBC implementation
optimal Ate pairing
Pairing based cryptography
pairing-based cryptography
PKC
Power measurement
pubcrawl
low-power electronics
public-key cryptography
Repudiation
resilience
Resiliency
sensors
simple power analysis
Software
system-on-chip
Zynq-7020 SoC
embedded electronic devices
Barreto-Naehrig curves
circuit optimisation
Clocks
composability
cryptographic services
cryptographic system
Cryptography
Differential Power Analysis
ECC
embedded
ARM Cortex A9 processor
energy consumption
field programmable gate arrays
Hardware
hardware-software co-design
hardware-software codesign
Human behavior
human factor
light-weight hardware/software co-design
lightweight devices
