A light-weight hardware/software co-design for pairing-based cryptography with low power and energy consumption
Title | A light-weight hardware/software co-design for pairing-based cryptography with low power and energy consumption |
Publication Type | Conference Paper |
Year of Publication | 2017 |
Authors | Salman, A., Diehl, W., Kaps, J. P. |
Conference Name | 2017 International Conference on Field Programmable Technology (ICFPT) |
Keywords | ARM Cortex A9 processor, Barreto-Naehrig curves, circuit optimisation, Clocks, composability, cryptographic services, cryptographic system, cryptography, Differential Power Analysis, ECC, Embedded, embedded electronic devices, energy consumption, field programmable gate arrays, Hardware, hardware-software co-design, hardware-software codesign, Human Behavior, human factor, light-weight hardware/software co-design, lightweight devices, low-power electronics, Metrics, Montgomery multiplier, multiplying circuits, open-source software PBC implementation, optimal Ate pairing, Pairing based cryptography, pairing-based cryptography, PKC, Power measurement, pubcrawl, public key cryptography, public-key cryptography, Repudiation, resilience, Resiliency, Sensors, simple power analysis, Software, system-on-chip, Zynq-7020 SoC |
Abstract | Embedded electronic devices and sensors such as smartphones, smart watches, medical implants, and Wireless Sensor Nodes (WSN) are making the "Internet of Things" (IoT) a reality. Such devices often require cryptographic services such as authentication, integrity and non-repudiation, which are provided by Public-Key Cryptography (PKC). As these devices are severely resource-constrained, choosing a suitable cryptographic system is challenging. Pairing Based Cryptography (PBC) is among the best candidates to implement PKC in lightweight devices. In this research, we present a fast and energy efficient implementation of PBC based on Barreto-Naehrig (BN) curves and optimal Ate pairing using hardware/software co-design. Our solution consists of a hardware-based Montgomery multiplier, and pairing software running on an ARM Cortex A9 processor in a Zynq-7020 System-on-Chip (SoC). The multiplier is protected against simple power analysis (SPA) and differential power analysis (DPA), and can be instantiated with a variable number of processing elements (PE). Our solution improves performance (in terms of latency) over an open-source software PBC implementation by factors of 2.34 and 2.02, for 256- and 160-bit field sizes, respectively, as measured in the Zynq-7020 SoC. |
URL | https://ieeexplore.ieee.org/document/8280149/ |
DOI | 10.1109/FPT.2017.8280149 |
Citation Key | salman_light-weight_2017 |
- public key cryptography
- Metrics
- Montgomery multiplier
- multiplying circuits
- open-source software PBC implementation
- optimal Ate pairing
- Pairing based cryptography
- pairing-based cryptography
- PKC
- Power measurement
- pubcrawl
- low-power electronics
- public-key cryptography
- Repudiation
- resilience
- Resiliency
- sensors
- simple power analysis
- Software
- system-on-chip
- Zynq-7020 SoC
- embedded electronic devices
- Barreto-Naehrig curves
- circuit optimisation
- Clocks
- composability
- cryptographic services
- cryptographic system
- Cryptography
- Differential Power Analysis
- ECC
- embedded
- ARM Cortex A9 processor
- energy consumption
- field programmable gate arrays
- Hardware
- hardware-software co-design
- hardware-software codesign
- Human behavior
- human factor
- light-weight hardware/software co-design
- lightweight devices